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PIC16C781/782 Data Sheet
8-Bit CMOS Microcontrollers with A/D, D/A, OPAMP, Comparators and PSMC
2001 Microchip Technology Inc.
Preliminary
DS41171A
Note the following details of the code protection feature on PICmicro(R) MCUs. * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
* * *
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, MPLAB and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICC, PICDEM, PICDEM.net, ICEPIC, Migratable Memory, FanSense, ECONOMONITOR, Select Mode and microPort are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Term Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2001, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS41171A - page ii
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
8-Bit CMOS Microcontrollers with A/D, D/A, OPAMP, Comparators and PSMC
Microcontroller Core Features:
* High performance RISC CPU * Only 35 single word instructions to learn * All single cycle instructions except for program branches which are two cycle * Direct, indirect and relative addressing modes - Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle Device PIC16C781 PIC16C782 Program Memory X14 1K 2K Data Memory X8 128 128
Microcontroller Core Features (Continued):
* Low power, high speed CMOS EPROM technology * Fully static design * Low power consumption: - < 2 mA @ 5V, 4 MHz - < 1 A typical standby current. Pin Diagram PDIP, Windowed CERDIP, SOIC, SSOP
RA0/AN0/OPA+ RA1/AN1/OPARA4/T0CKI RA5/MCLR/VPP VSS AVSS RA2/AN2/VREF2 RA3/AN3/VREF1 RB0/INT/AN4/VR RB1/AN5/VDAC *1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 20 19 18 17 16 15 14 13 12 11 RB3/AN7/OPA RB2/AN6 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT/T1CKI VDD AVDD RB7/C2/PSMC1B/T1G RB6/C1/PSMC1A RB5 RB4
PIC16C781/782
* 8-level deep hardware stack * Interrupt capability (up to 8 internal/external interrupt sources) * 16 I/O pins: - Individual direction control (13 pins) - Input only (3 pins), low leakage (2 pins) - Digital/Analog inputs (8 pins) * Programmable PORTB interrupt-on-change (8 pins) * Programmable PORTB weak pull-ups (8 pins) * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with a software enabled option and its own on-chip RC oscillator for reliable operation * Programmable Brown-out Reset (BOR) * Programmable Low Voltage Detection (LVD) * Internal/external MCLR * Programmable code protection * Power saving SLEEP mode * Selectable oscillator options: HS, XT, LP, EC, RC, INTRC (4 MHz/37 kHz) * In-Circuit Serial ProgrammingTM (ISCPTM) * Program Memory Read (PMR) capability * Four user programmable ID locations * Wide operating voltage range: - 2.5V to 5.5V for commercial and industrial temperature ranges - Extended temperature range available
Peripheral Features:
* Timer0: 8-bit timer/counter with 8-bit prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator, if INTRC oscillator mode selected * Analog-to-Digital Converter (ADC): - 8-bit resolution - Programmable 8-channel input - Internal voltages available for selfdiagnostics * Digital-to-Analog Converter (DAC): - 8-bit resolution - Reference from AVDD, VREF1, or VR module - Output configurable to VDAC pin, Comparators, and ADC reference * Operational Amplifier module (OPA): - Firmware initiated input offset voltage Auto Calibration module - Low leakage inputs - Programmable Gain Bandwidth Product (GBWP)
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 1
PIC16C781/782
Peripheral Features (Continued):
* Dual Analog Comparator module with: - Individual enable and interrupt bits - Programmable speed and output polarity - Fully configurable inputs and outputs - Reference from DAC, or VREF1/VREF2 - Low input offset voltage. * VR voltage reference module: - 3.072V +/- 0.7% @25C, AVDD = 5V - Configurable output to ADC reference, DAC reference, and VR pin - 5 mA sink/source * Programmable Switch Mode Controller module: - PWM and PSM modes - Programmable switching frequency - Configurable for either single or dual feedback inputs - Configurable single or dual outputs - Slope compensation output available in single output mode
Key Features PICmicroTM Mid-Range Reference Manual (DS33023) Operating Frequency RESETS (and Delays) Program Memory (14 bit words) Data Memory (bytes) Interrupts I/O Ports Timers Programmable Switch Mode Controller 8-bit Analog-to-Digital Module ADC channels 8-bit Digital-to-Analog Module Comparators Comparator Channels Operational Amplifier Voltage Reference Brown-out Reset Programmable Low Voltage Detect Instruction Set
PIC16C781
PIC16C782
DC - 20 MHz 1K 128 8 13 + 3 Input only 2 1 1 8 External, 2 Internal 1 2 4 (AN<7:4>) 1 1 Yes Yes 35 Instructions
DC - 20 MHZ 2K 128 8 13 + 3 Input only 2 1 1 8 External, 2 Internal 1 2 4 (AN<7:4>) 1 1 Yes Yes 35 Instructions
POR, BOR, MCLR, WDT (PWRT, OST) POR, BOR, MCLR, WDT (PWRT, OST)
DS41171A-page 2
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................ 11 3.0 I/O Ports .................................................................................................................................................................................... 25 4.0 Program Memory Read (PMR) .................................................................................................................................................. 47 5.0 Timer0 Module .......................................................................................................................................................................... 51 6.0 Timer1 Module with Gate Control .............................................................................................................................................. 55 7.0 Voltage Reference Module (VR) ................................................................................................................................................ 61 8.0 Programmable Low Voltage Detect Module (PLVD) ................................................................................................................. 63 9.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 69 10.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................... 79 11.0 Operational Amplifier (OPA) Module ......................................................................................................................................... 83 12.0 Comparator Module ................................................................................................................................................................... 89 13.0 Programmable Switch Mode Controller (PSMC) ....................................................................................................................... 99 14.0 Special Features of The CPU .................................................................................................................................................. 117 15.0 Instruction Set Summary ......................................................................................................................................................... 133 16.0 Development Support .............................................................................................................................................................. 141 17.0 Electrical Characteristics ......................................................................................................................................................... 147 18.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 167 19.0 Packaging Information ............................................................................................................................................................. 169 Index .................................................................................................................................................................................................. 175 On-Line Support................................................................................................................................................................................. 181 Reader Response .............................................................................................................................................................................. 182 PIC16C781/782 Product Identification System .................................................................................................................................. 183
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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2001 Microchip Technology Inc.
Preliminary
DS41171A-page 3
PIC16C781/782
NOTES:
DS41171A-page 4
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
1.0 DEVICE OVERVIEW
This document contains device-specific information. Additional information may be found in the PICmicroTM Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference manual should be considered a complementary document to this data sheet. The Reference manual is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. This data sheet covers two devices: PIC16C781 and PIC16C782. Both devices come in a variety of 20-pin packages. The following figures are block diagrams of the PIC16C781 and the PIC16C782.
FIGURE 1-1:
PIC16C781 BLOCK DIAGRAM
13
EPROM
Program Counter
Data Bus
8
PORTA RA0/AN0/OPA+ RA1/AN1/OPARA2/AN2/VREF2 RA3/AN3/VREF1 RA4/T0CKI RA5/MCLR/VPP RA6/OSC2/CLKOUT/T1CKI RA7/OSC1/CLKIN PORTB RB0/INT/AN4/VR RB1/AN5/VDAC RB2/AN6 RB3/AN7/OPA RB4 RB5 RB6/C1/PSMC1A RB7/C2/PSMC1B/T1G
Program
Memory
1K x 14
8 Level Stack (13-bit) Program Memory Read (PMR)
RAM
Program 14 Bus Instruction reg
File Registers 128 x 8 RAM 9 Addr
Addr MUX
Direct Addr
7
Indirect 8 Addr FSR reg
8 3
STATUS reg
Power-up Timer Instruction Decode & Control Timing Generation OSC2/ CLKOUT Internal RC Oscillator INTRC Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
MUX
OSC1/ CLKIN
ALU 8 W reg
AVDD, AVSS(1) VDD, VSS
Timer1 (TMR1) Voltage Reference (VR) Module Programmable Low Voltage Detect (PLVD)
Timer0 (TMR0)
Comparator (C1)
Comparator (C2)
8-bit ADC
Programmable Switch Mode Controller (PSMC)
OPAMP (OPA)
8-bit DAC
Note 1: AVDD and AVSS pins are used by the following modules: C1, C2, OPA, DAC, ADC, and VR.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 5
PIC16C781/782
FIGURE 1-2: PIC16C782 BLOCK DIAGRAM
13
EPROM
Program Counter
Data Bus
8
PORTA RA0/AN0/OPA+ RA1/AN1/OPARA2/AN2/VREF2 RA3/AN3/VREF1 RA4/T0CKI RA5/MCLR/VPP RA6/OSC2/CLKOUT/T1CKI RA7/OSC1/CLKIN PORTB RB0/INT/AN4/VR RB1/AN5/VDAC RB2/AN6 RB3/AN7/OPA RB4 RB5 RB6/C1/PSMC1A RB7/C2/PSMC1B/T1G
Program Memory
2K x 14
8 Level Stack (13-bit) Program Memory Read (PMR)
RAM
Program 14 Bus Instruction reg
File Registers 128 x 8 RAM 9 Addr
Addr MUX
Direct Addr
7
8
Indirect Addr
FSR reg 8 3 STATUS reg
Power-up Timer OSC1/ CLKIN Instruction Decode & Control Timing Generation OSC2/ CLKOUT Internal RC Oscillator INTRC Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
MUX
ALU 8 W reg
AVSS, AVSS(1) VDD, VSS
Timer1 (TMR1) Voltage Reference Module (VR) Programmable Low Voltage Detect PLVD
Timer0 TMR0
Comparator C1
Comparator C2
8-bit ADC
Programmable Switch Mode Controller PSMC
OPAMP OPA
8-bit DAC
Note 1: AVDD and AVSS pins are used for the following modules: C1, C2, OPA, DAC, ADC, and VR.
DS41171A-page 6
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
FIGURE 1-3: ANALOG SIGNAL MULTIPLEXING DIAGRAM
OPAON CMPEN GBWP OPA CHS<2:0> 3 RA0/AN0/OPA+ RA1/AN1/OPARA2/AN2/VREF2 RA3/AN3/VREF1 RB0/INT/AN4/VR RB1/AN5/VDAC RB2/AN6 RB3/AN7/OPA 0 1 2 ADRES RB7/C2 PSMC1B C2POL C2OUT C2R C2 3 4 5 6 7 EN CHS3 VR VDAC 0 EN 1 VREN 2 AN4 AN5 AN6 AN7 VREF1 VDAC 0 1 2 3 C1R 0 1 2 AN4 AN5 AN6 AN7 VREF2 VDAC DARS<1:0> DAC REGISTER 2 AVDD VREF1 VR N/C 0 1 2 3 0 1 2 3 0 1 DAON & DAOE
AN4
VCFG<1:0> AVDD VREF1 VR VDAC
0 1 2 3
ADCREF ADC
8
ADON GO/DONE VROE & VREN
VR REFERENCE
AN4
CHS0 C1CH<1:0> C1ON C1SP
C1OE
RB6/C1/ PSMC1A C1POL C1OUT
C1
C2CH<1:0>
C2OE
C2ON C2SP
DACREF 8 DAC
VDAC
DAON
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 7
PIC16C781/782
TABLE 1-1: PIC16C781/782 PINOUT DESCRIPTION
Function RA0 RA0/AN0/OPA+ AN0 OPA+ RA1 RA1/AN1/OPAAN1 OPARA2 RA2/AN2/VREF2 AN2 VREF2 RA3 RA3/AN3/VREF1 AN3 VREF1 RA4/T0CKI RA4 TOCKI RA5 RA5/MCLR/VPP MCLR VPP RA6 RA6/OSC2/CLKOUT/T1CKI OSC2 CLKOUT T1CKI RA7 RA7/OSC1/CLKIN OSC1 CLKIN RB0 RB0/INT/AN4/VR INT AN4 VR RB1 RB1/AN5/VDAC AN5 VDAC RB2/AN6 RB2 AN6 RB3 RB3/AN7/OPA AN7 OPA RB4 RB5 RB6/C1/PSMC1A RB4 RB5 RB6 C1 PSMC1A Input Type ST AN AN ST AN AN ST AN AN ST AN AN ST ST ST ST Power ST
-- --
Name
Output Type N/A
-- --
Description Port Input ADC Input OPAMP Non-inverting Input Port Input ADC Input OPAMP Inverting Input Bi-directional I/O ADC Input Comparator 2 Voltage Reference Input Bi-directional I/O ADC Input Comparator 1, ADC, DACREF Input Bi-directional I/O Timer0 Clock Input Port Input Master Clear Input Programming Voltage Bi-directional I/O Crystal/Resonator Fosc/4 Output Timer1 Clock Input Bi-directional I/O Crystal/Resonator External Clock Input Bi-directional I/O External Interrupt ADC, Comparator Input Internal Voltage Reference Output Bi-directional I/O ADC, Comparator Input DAC Output Bi-directional I/O ADC, Comparator Input Bi-directional I/O ADC, Comparator Input OPAMP Output Bi-directional I/O Bi-directional I/O Bi-directional I/O Comparator 1 Output PSMC Output 1A
N/A
-- --
CMOS
-- --
CMOS
-- --
OD
--
N/A
-- --
CMOS XTAL CMOS
--
ST ST XTAL ST TTL ST AN
--
CMOS
-- --
CMOS
-- --
AN CMOS
--
TTL AN
--
AN CMOS
--
TTL AN TTL AN
--
CMOS
--
AN CMOS CMOS CMOS CMOS CMOS
TTL TTL TTL
-- --
DS41171A-page 8
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
TABLE 1-1: PIC16C781/782 PINOUT DESCRIPTION (CONTINUED)
Function RB7 RB7/C2/PSMC1B/T1G C2 PSMC1B T1G AVDD AVSS VDD VSS Legend: ST = Schmitt Trigger XTAL = Crystal AVDD AVSS VDD VSS Input Type TTL --
--
Name
Output Type CMOS CMOS CMOS
--
Description Bi-directional I/O Comparator 2 Output PSMC Output 1B Timer 1 Gate Input Positive Supply for Analog Ground Reference for Analog Positive Supply for Logic and I/O pins Ground Reference for Logic and I/O pins OD = open drain Power = Power Supply TTL = Logic Level
ST Power Power Power Power
-- -- -- --
AN = Analog CMOS = CMOS Output
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 9
PIC16C781/782
NOTES:
DS41171A-page 10
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
2.0 MEMORY ORGANIZATION
FIGURE 2-2:
There are two memory blocks in each of these PICmicro(R) microcontrollers. Each block (program and data memory) has its own bus, so that concurrent access can occur. Additional information on device memory may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
PIC16C782 PROGRAM MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
2.1
Program Memory Organization
Stack Level 1 Stack Level 2
The PIC16C781/782 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16C781 has 1K x 14 words of program memory. The PIC16C782 has 2K x 14 words of program memory. Accessing a location above the physically implemented address causes a wraparound. The RESET vector is at 0000h and the interrupt vector is at 0004h.
Stack Level 8
RESET Vector
0000h
FIGURE 2-1:
PIC16C781 PROGRAM MEMORY MAP AND STACK
PC<12:0>
Interrupt Vector On-Chip Program Memory Page 0
0004h 0005h 07FFh 0800h
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2 1FFFh Stack Level 8
2.2
RESET Vector 0000h
Data Memory Organization
Interrupt Vector On-Chip Program Memory Page 0
0004h 0005h 03FFh 0400h
The data memory is partitioned into multiple banks, which contain the General Purpose Registers and the Special Function Registers. Bits RP0 and RP1 are bank select bits. RP1 RP0 (STATUS<6:5>) = 00 Bank0 = 01 Bank1 = 10 Bank2 = 11 Bank3 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are the General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank are mirrored in another bank for code reduction and quicker access.
1FFFh
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 11
PIC16C781/782
FIGURE 2-3: REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(*) 80h OPTION_REG 81h 82h PCL 83h STATUS 84h FSR 85h TRISA 86h TRISB 87h 88h 89h 8Ah PCLATH 8Bh INTCON PIE1 8Ch 8Dh 8Eh PCON 8Fh 90h 91h 92h 93h 94h WPUB 95h IOCB 96h 97h 98h 99h 9Ah 9Bh REFCON LVDCON 9Ch ANSEL 9Dh 9Eh 9Fh ADCON1 General Purpose Register 32 Bytes A0h File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTB 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h File Address Indirect addr.(*) 180h OPTION_REG 181h 182h PCL 183h STATUS 184h FSR 185h 186h TRISB 187h 188h 189h 18Ah PCLATH 18Bh INTCON 18Ch PMCON1 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON PIR1 TMR1L TMR1H T1CON
PCLATH INTCON PMDATL PMADRL PMDATH PMADRH CALCON PSMCCON0 PSMCCON1
CM1CON0 CM2CON0 CM2CON1 OPACON DAC DACON0
ADRES ADCON0
General Purpose Register 96 Bytes
BFh
accesses 70h-7Fh 7Fh Bank 0 Bank 1
EFh F0h FFh
accesses 70h-7Fh Bank 2
170h 17Fh
accesses 70h-7Fh Bank 3
1F0h 1FFh
Unimplemented data memory locations, read as '0'. * Not a physical register.
DS41171A-page 12
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
2.2.1 GENERAL PURPOSE REGISTER FILE 2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1.
The register file can be accessed either directly, or indirectly, through the File Select Register (FSR).
TABLE 2-1:
Address Bank 0 00h(2) 01h 02h(2) 03h(2) 04h(2) 05h 06h 07h 08h 09h 0Ah(1, 2) 0Bh(2) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note INDF TMR0 PCL STATUS FSR PORTA PORTB -- -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON -- -- -- -- -- -- -- -- -- -- -- -- -- ADRES ADCON0 Name
PIC16C781/782 SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on Page:
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
23 51 23 17 23 26 35 -- -- -- 23 19 21 -- 55 55 57 -- -- -- -- -- -- -- -- -- -- -- -- -- 71 70
Indirect Data Memory Address Pointer RA7 RB7 RA6 RB6 RA5 RB5 RA4 RB4 RA3 RB3 RA2 RB2 RA1 RB1 RA0 RB0
xxxx 0000 xxxx 0000
Unimplemented Unimplemented Unimplemented -- GIE LVDIF -- PEIE ADIF -- T0IE C2IF Write Buffer for the upper 5 bits of the Program Counter INTE C1IF RBIE -- T0IF -- INTF -- RBIF TMR1IF
-- -- --
---0 0000 0000 000x 0000 ---0
Unimplemented Holding register for the Least Significant Byte of the 16-bit TMR1 Register Holding register for the Most Significant Byte of the 16-bit TMR1 Register -- TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
--
xxxx xxxx xxxx xxxx -000 0000
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented ADC Result Register ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON
-- -- -- -- -- -- -- -- -- -- -- -- --
xxxx xxxx 0000 0000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. Shaded locations are unimplemented, read as `0'. 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. See Section 2.9 for more detail. 2: These registers can be addressed from any bank.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 13
PIC16C781/782
TABLE 2-1:
Address Bank 1 80h(2) 81h 82h(2) 83h
(2)
PIC16C781/782 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on Page:
Name
INDF OPTION_REG PCL STATUS FSR TRISA TRISB -- -- -- PCLATH INTCON PIE1 -- PCON -- -- -- -- -- WPUB IOCB -- -- -- -- REFCON LVDCON ANSEL -- ADCON1
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 1111 1111 0000 0000
23 18 23 17 23 26 35 -- -- -- 23 19 20 22, 120 -- -- -- -- -- -- 36 36 -- -- -- -- 61 66 25 -- 71
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0001 1xxx xxxx xxxx 1111 1111 1111 1111
84h(2) 85h 86h 87h 88h 89h 8Ah(1,2) 8Bh(2) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note
Indirect Data Memory Address Pointer PORTA Data Direction Register PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE LVDIE -- PEIE ADIE -- T0IE C2IE Write Buffer for the upper 5 bits of the Program Counter INTE C1IE RBIE -- T0IF -- INTF -- RBIF TMR1IE
-- -- --
---0 0000 0000 000x 0000 ---0
Unimplemented -- -- -- WDTON OSCF -- POR BOR
---q 1-qq
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented PORTB Weak Pull-up Control PORTB Interrupt-on-Change Control Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- -- BGST -- LVDEN VREN LV3 VROE LV2 -- LV1 LV0
-- -- -- -- -- --
1111 1111 1111 0000
-- -- -- --
---- 00---00 0101 1111 1111
Analog Channel Select Unimplemented -- -- VCFG1 VCFG0 -- -- -- --
--
--00 ----
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. Shaded locations are unimplemented, read as `0'. 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. See Section 2.9 for more detail. 2: These registers can be addressed from any bank.
DS41171A-page 14
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
TABLE 2-1:
Address Bank 2 100h(2) 101h 102h(2) 103h(2) 104h(2) 105h 106h 107h 108h 109h 10Bh(2) 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note DAC DACON0 INDF TMR0 PCL STATUS FSR -- PORTB -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
PIC16C781/782 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on Page:
Name
23 51 23 17 23 -- 35 -- -- -- 23 19 48 48 47 48 85 104 104 -- -- -- -- -- -- 91 93 94 84 -- 79 79
Indirect Data Memory Address Pointer Unimplemented RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
--
xxxx 0000
Unimplemented Unimplemented Unimplemented -- GIE PMD7 PMA7 -- -- CAL -- PEIE PMD6 PMA6 -- -- CALERR -- T0IE PMD5 PMA5 PMD13 -- CALREF MINDC1 S1BPOL Write Buffer for the upper 5 bits of the Program Counter INTE PMD4 PMA4 PMD12 Reserved -- MINDC0 -- RBIE PMD3 PMA3 PMD11 Reserved -- MAXDC1 SCEN T0IF PMD2 PMA2 PMD10 PMA10 -- MAXDC0 SMCOM INTF PMD1 PMA1 PMD9 PMA9 -- DC1 PWM/PSM RBIF PMD0 PMA0 PMD8 PMA8 -- DC0 SMCCS
-- -- --
---0 0000 0000 000x 0000 0000 xxxx xxxx --00 0000 ---x xxxx 000- ---0000 0000 000- 0000
10Ah(1,2) PCLATH INTCON PMDATL PMADRL PMDATH PMADRH CALCON PSMCCON0 PSMCCON1 -- -- -- -- -- -- CM1CON0 CM2CON0 CM2CON1 OPACON --
SMCCL1 SMCCL0 SMCON S1APOL
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented C1ON C2ON C1OUT C2OUT C1OE C2OE -- -- C1POL C2POL -- -- C1SP C2SP -- -- C1R C2R -- -- C1CH1 C2CH1 -- -- C1CH0 C2CH0 C2SYNC GBWP
-- -- -- -- -- --
0000 0000 0000 0000 00-- ---0 00-- ---0
MC1OUT MC2OUT OPAON CMPEN
Unimplemented DA7 DAON DA6 DAOE DA5 -- DA4 -- DA3 -- DA2 -- DA1 DARS1 DA0 DARS0
--
0000 0000 00-- --00
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. Shaded locations are unimplemented, read as `0'. 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. See Section 2.9 for more detail. 2: These registers can be addressed from any bank.
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PIC16C781/782
TABLE 2-1:
Address Bank 3 180h(2) 181h 182h(2) 183h
(2)
PIC16C781/782 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on Page:
Name
INDF OPTION_REG PCL STATUS FSR -- TRISB -- -- --
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 1111 1111 0000 0000
23 18 23 17 23 -- 35 -- -- -- 23 19 47 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0001 1xxx xxxx xxxx
184h(2) 185h 186h 187h 188h 189h 18Bh(2) 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note
Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE Reserved -- PEIE -- -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE -- T0IF -- INTF -- RBIF RD
--
1111 1111
-- -- --
---0 0000 0000 000x 1--- ---0
18Ah(1,2) PCLATH INTCON PMCON1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. Shaded locations are unimplemented, read as `0'. 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. See Section 2.9 for more detail. 2: These registers can be addressed from any bank.
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2.3 STATUS Register
The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, or C bits, the write to these three bits is disabled. These bits are set or cleared according to the device logic. The TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as the destination may be different than intended. For example, CLRF STATUS clears the upper three bits and sets the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, since these instructions do not affect the Z, C, or DC bits from the STATUS register. For other instructions not affecting any status bits, see the "Instruction Set Summary." Note: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS REGISTER (STATUS: 03h, 83h, 103h, 183h)
R/W-0 IRP bit7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
bit 7
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP<1:0>: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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2.4 OPTION_REG Register
Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. The OPTION_REG register is a readable and writable register which contains various control bits to configure: * TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler) * External INT interrupt * TMR0 * Weak pull-ups on PORTB
REGISTER 2-2:
OPTION REGISTER (OPTION_REG: 81h, 181h)
R/W-1 RBPU bit7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
bit 7
RBPU: PORTB Pull-up Enable bit(1) 1 = PORTB weak pull-ups are disabled 0 = PORTB weak pull-ups are enabled by the WPUB register INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
Bit Value
000 001 010 011 100 101 110 111
bit 6
bit 5
bit 4
bit 3
bit 2-0
TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
Note 1: Individual weak pull-ups on RB pins can be enabled/disabled from the weak pull-up PORTB register (WPUB). Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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2.5 INTCON Register
Note: The INTCON register is a readable and writable register which contains: * Enable and interrupt flag bits for TMR0 register overflow * Enable and interrupt flag bits for the external interrupt (INT) * Enable and interrupt flag bits for PORTB Interrupt-on-Change (IOCB) * Peripheral interrupt enable bit * Global interrupt enable bit Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-3:
INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 T01E R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit(1) 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit(1) 1 = When at least one of the RB7:RB0 pins changed state (must be cleared in software) 0 = None of the RB7:RB0 pins have changed state Note 1: Individual RB pin interrupt-on-change can be enabled/disabled from the Interrupton-Change PORTB register (IOCB). Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.6 PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt (see Register 2-3). The PIE1 register contains the individual enable bits for the peripheral interrupts.
REGISTER 2-4:
PERIPHERAL INTERRUPT ENABLE REGISTER (PIE1: 8Ch)
R/W-0 LVDIE bit7 R/W-0 ADIE R/W-0 C2IE R/W-0 C1IE U-0 -- U-0 -- U-0 -- R/W-0 TMR1IE bit0
bit 7
LVDIE: Low Voltage Detect Interrupt Enable bit 1 = LVD interrupt is enabled 0 = LVD interrupt is disabled ADIE: Analog-to-Digital Converter Interrupt Enable bit 1 = Enables the Analog-to-Digital Converter interrupt 0 = Disables the Analog-to-Digital Converter interrupt C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt Unimplemented: Read as '0' TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3-1 bit 0
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2.7 PIR1 Register
Note: This register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-5:
PERIPHERAL INTERRUPT REGISTER (PIR1 0Ch)
R/W-0 LVDIF bit7 R/W-0 ADIF R/W-0 C2IF R/W-0 C1IF U-0 -- U-0 -- U-0 -- R/W-0 TMR1IF bit 0
bit 7
LVDIF: Low Voltage Detect Interrupt Flag bit 1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software) 0 = The supply voltage is greater than the specified LVD voltage ADIF: Analog-to-Digital Converter Interrupt Flag bit 1 = An ADC conversion completed (must be cleared in software) 0 = The ADC conversion is not complete C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator C2 input has crossed the threshold (must be cleared in software) 0 = Comparator C2 input has not crossed the threshold C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator C1 input has crossed the threshold (must be cleared in software) 0 = Comparator C1 input has not crossed the threshold Unimplemented: Read as `0' TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3-1 bit 0
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PIC16C781/782
2.8 PCON Register
Typical Time Inactive Direction of Change Minimum 4 MHz 37 kHz 37 kHz4 MHz Note: 100 s 1.25 s Maximum 300 s 3.25 s The Power Control (PCON) register contains two flag bits to allow determination of the source of the most recent RESET: * Power-on Reset (POR) * External MCLR Reset * Power Supply Brown-out (BOR) Reset The Power Control register also contains frequency select bits for the INTRC oscillator and the WDT software enable bit. Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Configuration word).
When changing the internal oscillator speed (i.e., the OSCF bit, INTRC mode), the processor will be inactive during the oscillator frequency change.
REGISTER 2-6:
POWER CONTROL REGISTER (PCON: 8Eh)
U-0 -- bit 7 U-0 -- U-0 -- R/W-q WDTON R/W-1 OSCF U-0 -- R/W-q POR R/W-q BOR bit 0
bit 7-5 bit 4
Unimplemented: Read as '0' WDTON: WDT Software Enable bit If WDTE bit (Configuration Word <3>) = 1: This bit is not writable, always reads `1' If WDTE bit (Configuration Word <3>) = 0: 1 = WDT is enabled 0 = WDT is disabled
bit 3
OSCF: Oscillator Speed INTRC Mode bit 1 = 4 MHz typical 0 = 37 kHz typical All other oscillator modes (X = Ignored) Unimplemented: Read as '0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred Legend: q = Value depends on conditions R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 2 bit 1
bit 0
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2.9 PCL and PCLATH 2.11 INDF
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13-bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register occur through the PCLATH register. The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is known as indirect addressing. Reading INDF itself, indirectly (FSR = 0), produces 00h. Writing to the INDF register indirectly results in a no operation (although STATUS bits may be affected). A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-1.
2.9.1
PROGRAM MEMORY PAGING
PIC16C781/782 devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When performing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When performing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. A return instruction pops a PC address off the stack onto the PC register. Therefore, manipulation of the PCLATH<4:3> bits is not required for the return instructions (which POPs the address from the stack).
EXAMPLE 2-1:
HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
NEXT
movlw movwf clrf incf btfss goto :
CONTINUE
2.10
Stack
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-5.
The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Mid-range devices have an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW, or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
FIGURE 2-4:
PCH 12 87 PCLATH<4:0> 5 PCLATH 12 PCH 1110
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 0 Instruction with PCL as Destination ALU
8
PCL 87 11 Opcode <10:0> 0 GOTO, CALL
PCLATH<4:3> 2 PCLATH
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Preliminary
DS41171A-page 23
PIC16C781/782
FIGURE 2-5: DIRECT/INDIRECT ADDRESSING
Indirect Addressing
0 IRP 7 FSR Register 0
Direct Addressing
RP1:RP0 6 From Opcode
Bank Select
Location Select 00 00h 01 80h 10 100h 11 180h
Bank Select
Location Select
Data Memory(1)
7Fh Bank 0
FFh Bank 1
17Fh Bank 2
1FFh Bank 3
Note 1: For register file map detail, see Figure 2-3.
2.12
Effect of RESET on Core Registers
Refer to Table 2-2 for the effect of a RESET operation on core registers.
TABLE 2-2:
Address Name
EFFECT OF RESET ON CORE REGISTERS
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS(1)
Bank 0 00h 02h 04h 0Ah 0Ch Bank 1 81h 83h 8Bh 8Ch 8Eh Legend: Note OPTION_REG STATUS INTCON PIE1 PCON RBPU IRP GIE LVDIE -- INTEDG RP1 PEIE ADIE -- T0CS RP0 T0IE C2IE -- T0SE TO INTE C1IE WDTON PSA PD RBIE -- OSCF PS2 Z T0IF -- -- PS1 DC INTF -- POR PS0 C RBIF TMR1IE BOR
xxxx xxxx 1111 1111 0001 1xxx 000q quuu 0000 000x 0000 000u 0000 ---0 0000 ---0 ---q 1-qq ---q 1-qq
INDF PCL FSR PCLATH PIR1
Addressing this location uses contents of FSR to address data memory (not a physical register) Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer -- LVDIF -- ADIF -- C2IF Write Buffer for the upper 5 bits of the Program Counter C1IF -- -- -- TMR1IF
0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu ---0 0000 ---0 0000 0000 ---0 0000 ---0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. Shaded locations are unimplemented, read as `0'. 1: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
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3.0 I/O PORTS
Most pins for the I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range Reference Manual (DS33023) to prevent unnecessary current drawn from the power supply. The Analog Select register (ANSEL) allows the user to individually select the Digital/Analog mode on these pins. When the Analog mode is active, the port pin always reads as a logic 0.
3.1
I/O Port Analog/Digital Mode
Note 1: On a Power-on Reset, the ANSEL register configures these mixed signal pins as Analog mode: RA<3:0>, RB<3:0>. 2: If a pin is configured as Analog mode, the pin always reads '0', even if the digital output is active.
The PIC16C781/782 has two I/O ports: PORTA and PORTB. Some of these port pins are mixed signal (can be digital or analog). When an analog signal is present on a pin, the pin must be configured as an analog input
REGISTER 3-1:
ANALOG SELECT REGISTER (ANSEL: 9Dh)
R/W-1 ANS7 bit 7 R/W-1 ANS6 R/W-1 ANS5 R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0
bit 7-0
ANS<7:0>: Select Analog Input Function on AN<7:0> bits 1 = Analog input 0 = Digital I/O Note: Setting a pin to an analog input disables the digital input buffer. The corresponding TRIS bit should be set to input mode when using pins as analog inputs.
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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3.2 PORTA and the TRISA Register
EXAMPLE 3-1:
;* ;* ;* ;* ;* ;* ;* ;* ;*
INITIALIZING PORTA
PORTA is an 8-bit wide, bi-directional port with the exception of RA0, RA1 and RA5, which are inputs only. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) makes the corresponding PORTA pin an input (i.e., disables the digital output). Clearing a TRISA bit (= 0) makes the corresponding PORTA pin an output (i.e., disables the digital output). Reading the PORTA register reads the status of the pins, whereas writing to it, writes to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is then modified and written to the port data latch. Pins RA<3:0> are multiplexed with analog functions: * Analog inputs AN<3:0> to the A/D Converter. * VREF1 and VREF2 inputs to the comparators. * OPAMP inverting/non-inverting inputs.
This code block will configure PORTA as follows RA<7:4> digital outputs RA<3:2> digital inputs RA<1:0> analog inputs RB<3:0> digital I/O Note 1: RB<3:0> configured as digital I/O Note 2: RA<7:6> availability depends on the oscillator selection BANKSEL CLRF BANKSEL MOVLW MOVWF MOVLW MOVWF ; ; ; TRISA ; B'00001111'; ; TRISA ; ; B'00000011'; ; ANSEL ; ; PORTA PORTA Select Bank 0 Preset PORTA data reg Select Bank 1 Digital I/O config data Configure PORTA digital Analog I/O config data Configure PORTA analog
Note:
When the analog peripherals are using any of these pins as analog input/output, the ANSEL register must have the proper value to individually select the Analog mode of the corresponding pins.
3.2.1
TRISA, ANSEL, AND CONTROL PRECEDENCE
Pins RA<7:4> are multiplexed with digital functions: * Pin RA4 is multiplexed with the TMR0 module clock input. * Pin RA5 is multiplexed with the device RESET (MCLR) and programming input (VPP) function. * Pins RA6 and RA7 are multiplexed with the oscillator/clock I/O functions. RA6 can also be configured as the TMR1 clock input. PORTA has the following I/O characteristics: * RA0, RA1, and RA5 are input only. * RA4 is an open drain output. All other PORTA pins have full CMOS buffer outputs. * All PORTA pins have Schmitt trigger inputs.
The ANSEL and TRISA registers are the primary software controls for the configuration of PORTA pins. TRISA bits tri-state the output drivers of PORTA, and ANSEL register bits control the digital input buffers. It is important to program both registers when configuring a mixed signal port pin, as most peripherals cannot override the TRISA and ANSEL registers control. Even if a peripheral has the ability to override control of the TRISA and ANSEL registers, it is good programming practice to program both registers appropriately. There are specific cases in which the TRISA and ANSEL registers can be overridden by a peripheral or a configuration bit, see Figures 3-1 through 3-8 for details. Note: Crystal (LP, XT and HS) oscillator configurations use pin RA6/OSC2/CLKOUT/ T1CKI as OSC2. In these modes, setting or clearing TRISA<6> will have no effect and the pin will read as a zero (0).
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FIGURE 3-1: BLOCK DIAGRAM OF RA0/AN0/OPA+ PIN
VDD RD ANSEL RA0/AN0/OPA+
RD TRISA
VSS
VSS
Data Bus ANSEL Reg. D Q
WR ANSEL
CK
Q Data Reg. Q D
EN RD PORTA
Analog Function Enable AN0/OPA+ (see Figure 1-3)
ANSEL<0> 0 1
TRISA<0> x x
FUNCTION Digital In Analog In
PORTA<0> READ Pin 0
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Preliminary
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PIC16C781/782
FIGURE 3-2: BLOCK DIAGRAM OF RA1/AN1/OPA- PIN
VDD RD ANSEL RA1/AN1/OPA-
RD TRISA
VSS
VSS
Data Bus
ANSEL Reg. D Q
WR ANSEL
CK
Q Data Reg. Q D
EN RD PORTA
Analog Function Enable AN1/OPA- (see Figure 1-3)
ANSEL<1> 0 1
TRISA<1> x x
FUNCTION Digital In Analog In
PORTA<1> READ Pin 0
DS41171A-page 28
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
FIGURE 3-3:
RD ANSEL
BLOCK DIAGRAM OF RA2/AN2/VREF2 PIN
Data Bus Data Reg.
D WR PORTA Q
VDD
CK Q
VDD RA2/AN2/VREF2
P N
TRIS Reg. D WR TRISA Q
CK
Q
VSS
VSS
RD TRISA ANSEL Reg. D WR ANSEL CK Q
Q Data Reg. Q D
EN RD PORTA Analog Function Enable AN2/VREF2 (see Figure 1-3)
ANSEL<2> 0 0 1
TRISA<2> 1 0 x
FUNCTION Digital In Digital Out Analog In
PORTA<2> READ Pin Pin 0
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 29
PIC16C781/782
FIGURE 3-4:
RD ANSEL
BLOCK DIAGRAM OF RA3/AN3/VREF1 PIN
Data Bus Data Reg.
D WR PORTA Q
VDD
CK Q
VDD RA3/AN3/VREF1
P N
TRIS Reg. D WR TRISA Q
CK
Q
VSS
VSS
RD TRISA ANSEL Reg. D WR ANSEL CK Q Q Data Reg. Q D
EN RD PORTA Analog Function Enable AN3/VREF1 (see Figure 1-3)
ANSEL<3> 0 0 1
TRISA<3> 1 0 x
FUNCTION Digital In Digital Out Analog In
PORTA<3> READ Pin Pin 0
DS41171A-page 30
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
FIGURE 3-5: BLOCK DIAGRAM OF RA4/T0CKI PIN
Data Reg. Data Bus D Q
WR PORTA
CK
Q
RA4/T0CKI
TRIS Reg. D Q N
WR TRISA
CK
Q
Vss Vss
RD TRISA
Data Reg. Q D
EN RD PORTA TMR0 Clock Input
TRISA<4> 1 0 0
PORTA<4> x 0 1
FUNCTION Digital In 0 Output Hi-Z Output
PORTA<4> READ Pin Pin Pin
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 31
PIC16C781/782
FIGURE 3-6:
MCLRE RA5/MCLR/VPP To MCLR Circuit MCLR Filter
BLOCK DIAGRAM OF RA5/MCLR/VPP PIN
Program Mode HV Detect VSS
Data Bus
RD TRISA
VSS
Data Reg. Q D
EN RD PORTA
MCLRE(1) Internal External
TRISA<5> x x
FUNCTION Digital In MCLR
PORTA<5> READ Pin 0
Note 1: See Configuration Word <5>, Register 14-1.
DS41171A-page 32
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
FIGURE 3-7: BLOCK DIAGRAM OF RA6/OSC2/CLKOUT/T1CKI PIN
(INTRC w/ CLKOUT) or (RC w/ CLKOUT)
CLKOUT (FOSC/4) 1 0
OSC1 FOSC<2:0>(1) T1OSCEN
Oscillator Circuit VDD
RA6/OSC2/CLKOUT/T1CKI
Data Reg. Data Bus D Q VDD P (INTRC) or (RC)
(see Table)
WR PORTA
VSS
CK
Q
TRIS Reg. D Q WR TRISA
CK
Q (INTRC w/ CLKOUT) or (RC w/ CLKOUT)
N (INTRC w/o CLKOUT) or (RC w/o CLKOUT) or (EC) VSS
RD TRISA Data Reg. Q D EN RD PORTA T1CKI
OSC MODE(1) LP, XT, HS RC, INTRC w/ CLKOUT INTRC w/o CLKOUT INTRC w/o CLKOUT RC w/o CLKOUT EC N/A = Not Available
TMR1 OSCILLATOR N/A N/A Enabled Disabled N/A N/A w/ = with w/o = without
PIN FUNCTION OSC2 CLKOUT OSC2 (TMR1) Digital I/O Digital I/O Digital I/O
T1CKI N/A N/A N/A Available Available Available
PORTA<6> READ 0 0 0 Pin Pin Pin
Note 1: See Configuration Word FOSC<2:0>, Register 14-1.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 33
PIC16C781/782
FIGURE 3-8: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN
OSC2 Oscillator Circuit
FOSC<2:0>(1) T1OSCEN
To Chip Clock Drivers Data Reg. Data Bus
D Q VDD EC Mode WR PORTA CK Q P
VDD RA7/OSC1/CLKIN
TRIS Reg. D Q WR TRISA
N
VSS
CK
Q
VSS (INTRC w/ CLKOUT) or (INTRC w/o CLKOUT)
RD TRISA
Data Reg. Q D EN RD PORTA
OSC MODE(1) LP, XT, HS RC EC INTRC INTRC N/A = Not Available
TMR1 OSCILLATOR N/A N/A N/A Enabled Disabled
PIN FUNCTION OSC1 OSC1 CLKIN OSC1 (TMR1) Digital I/O
PORTA<7> READ 0 0 0 0 Pin
Note 1: See Configuration Word FOSC<2:0>, Register 14-1.
TABLE 3-1:
Address 05h 85h 9Dh Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS
Name
PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 uuuu 0000 TRISA PORTA Data Direction Register 1111 1111 1111 1111 ANSEL AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 1111 1111 1111 1111 x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTA.
DS41171A-page 34
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
3.3 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) makes the corresponding PORTB pin an input (i.e., puts the corresponding output driver into a Hi-Impedance mode). Clearing a TRISB bit (= 0) makes the corresponding PORTB pin an output (i.e., puts the contents of the output latch on the selected pin. Pin RB2 is multiplexed with the analog function ADC/ Comparator Input AN6. When the pin is used as an analog input, the ANSEL register must have bit 6 to select the Analog mode for the pin. The RB3 pin is multiplexed with two analog functions: ADC/Comparator Analog Input AN7, and the output of the OPA module. When the pin is used as analog I/O, the ANSEL register must have bit 7 set to select the Analog mode of the pin. Pins RB<7:6> are multiplexed with the outputs of the two on-board comparators, the outputs of the PSMC module, and the clock gate input for Timer1. Note, when enabled, these peripherals override the PORTB data register; however, TRISB retains control of output drivers. Therefore, TRISB<7:6> must be programmed appropriately for Comparator and PSMC outputs to operate.
EXAMPLE 3-2:
INITIALIZING PORTB
;* This code block will configure PORT B ;* as follows ;* RB<7:6> analog inputs ;* RB<5:4> digital inputs ;* RB<3:2> digital inputs ;* RB<1:0> digital inputs ;* RA<3:0> digital I/O BANKSEL CLRF BANKSEL MOVLW MOVWF MOVLW MOVWF ; ; ; TRISB ; B'11001111' ; ; TRISB ; ; B'00000011' ; ; ANSEL ; ; PORTB PORTB Select Bank 0 Preset PORTB data reg. Select Bank 1 Digital I/O config data Configure PORTB digital Analog I/O config data Configure PORTB analog
3.3.1
PORTB WEAK PULL-UP
Each of the PORTB pins has an internal weak pull-up resistance, which can be individually enabled from the WPUB register. A single global enable bit, RBPU (OPTION_REG<7>), can turn on/off all of the selected pull-ups. Clearing the RBPU bit (OPTION_REG<7>) enables the weak pull-up resistors (see Register 3-2). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
3.3.2
PORTB INTERRUPT-ON-CHANGE
The RB0 pin can be configured as: * * * * Digital I/O ADC/Comparator Analog Input (AN4) External Interrupt (INT) Voltage Reference Output (VR)
When the pin is used as an analog I/O, the ANSEL register must have bit 4 set to configure the RB0 pin as an analog input. Pin RB1 is multiplexed with two analog functions: ADC/ Comparator Analog Input AN5, and the output of the DAC. When the pin is used as an analog I/O, the ANSEL register must have bit 5 set to configure the RB1 pin as an analog I/O.
Each of the PORTB pins, if configured as input, has the ability to generate an interrupt-on-change. To enable the interrupt-on-change feature, the corresponding bit must be set in the IOCB register (see Register 3-3). The RBIE bit in the INTCON register functions as a global enable bit to turn on/off the interrupt-on-change feature. The selected inputs are compared to the old value latched on the last read of PORTB. The "mismatch" outputs are OR-ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). The IOCB interrupt can also awaken the device from SLEEP. The user, in the Interrupt Service Routine, must clear the interrupt in the following manner: a) A read or write to PORTB. This copies the current state into the latch and ends the mismatch condition. Clear flag bit RBIF.
b)
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 35
PIC16C781/782
REGISTER 3-2:
WEAK PULL-UP PORTB REGISTER (WPUB: 95h)
R/W-1 WPUB7 bit7 bit 7-0 WPUB<7:0>: PORTB Weak Pull-Up Control bits 1 = Weak pull-up enabled for corresponding pin 0 = Weak pull-up disabled for corresponding pin Note 1: For the WPUB register setting to take effect, the RBPU bit in the OPTION_REG register must be cleared. 2: The weak pull-up device is automatically disabled if the pin is in output mode, i.e., (TRISB = 0) for corresponding pin. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-1 WPUB6 R/W-1 WPUB5 R/W-1 WPUB4 R/W-1 WPUB3 R/W-1 WPUB2 R/W-1 WPUB1 R/W-1 WPUB0 bit0
REGISTER 3-3:
INTERRUPT-ON-CHANGE PORTB REGISTER (IOCB: 96h)
R/W-1 IOCB7 bit7 R/W-1 IOCB6 R/W-1 IOCB5 R/W-1 IOCB4 R/W-0 IOCB3 R/W-0 IOCB2 R/W-0 IOCB1 R/W-0 IOCB0 bit0
bit 7-0
IOCB<7:0>: Interrupt-on-Change PORTB Control bits 1 = Interrupt-on-change enabled for corresponding pin 0 = Interrupt-on-change disabled for corresponding pin Note 1: The interrupt enable bits, GIE and RBIE in the INTCON register, must be set for individual interrupts to be recognized. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
3.3.3
TRISB, ANSEL, AND CONTROL PRECEDENCE
The ANSEL and TRISB registers are the primary controls for the configuration of PORTB pins. TRISB tristates the output drivers of PORTB, and the ANSEL register disables the input buffers. It is important to program both registers when configuring a port pin, since most peripherals do not have precedence over the TRISB and ANSEL registers' control of the pin. Even if a peripheral has the ability to override the control of the TRISB and ANSEL registers, it is good practice to program both registers appropriately.
Note 1: Upon RESET, the ANSEL register configures the RB<3:0> pins as analog inputs. 2: When programmed as analog inputs, RB<3:0> pins will read as `0'. 3: There are specific cases in which the functions of the TRISB and ANSEL registers can be overridden by a peripheral or configuration word (see Figure 3-9 through Figure 3-16 for details).
DS41171A-page 36
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
FIGURE 3-9:
VREN VROE VR Output
WPUB Reg.
BLOCK DIAGRAM OF RB0/INT/AN4/VR PIN
Data Bus WR WPUB RD WPUB
D
Q
CK
Q RBPU
VDD P Weak
Pull-up
PORTB Reg.
D Q
VDD P
VDD RB0/INT/AN4/VR
WR PORTB
CK
Q
TRIS Reg.
D Q
N
WR TRISB
CK
Q
VSS
VSS
RD TRISB ANSEL Reg. D WR ANSEL CK Q Q TTL IOCB Reg.
D Q
RD ANSEL
WR IOCB
CK
Q
Set RBIF
...
From other RB<7:0> pins
Q D
Q
D EN Q1
RD IOCB
Q
D EN
EN EN
Q3
RD PORTB
INT Input Analog Function Enable AN4/VR
VREN & VROE 0 0 0 1
ANSEL<4> 0 0 1 x
TRISB<0> 1 0 x x
FUNCTION Digital In Digital Out Analog In Analog Out
PORTB<0> READ Pin Pin 0 0
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 37
PIC16C781/782
FIGURE 3-10:
DAON DAOE WPUB Reg. Data Bus WR WPUB RD WPUB
D Q
BLOCK DIAGRAM OF RB1/AN5/VDAC PIN
VDAC Output
CK
Q
VDD
RBPU
P Weak PORTB Reg.
D Q
Pull-up
VDD
P
VDD RB1/AN5/VDAC
WR PORTB
CK
Q
TRIS Reg.
D Q
N
WR TRISB
CK
Q
VSS
VSS
RD TRISB ANSEL Reg. D WR ANSEL CK Q Q TTL IOCB Reg.
D Q
RD ANSEL
WR IOCB
CK
Q
Set RBIF
...
From other RB<7:0> pins
Q
D
Q
D EN Q1
RD IOCB
EN EN
Q
D EN
Q3
RD PORTB
Analog Function Enable AN5/VDAC
DAON & DAOE 0 0 0 1
ANSEL<5> 0 0 1 x
TRISB<1> 1 0 x x
FUNCTION Digital In Digital Out Analog In Analog Out
PORTB<1> READ Pin Pin 0 0
DS41171A-page 38
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
FIGURE 3-11:
Data Bus WR WPUB
BLOCK DIAGRAM OF RB2/AN6 PIN
WPUB Reg.
D Q
CK
Q RBPU
VDD
P Weak
RD WPUB PORTB Reg.
D Q
Pull-up
VDD P
VDD RB2/AN6
WR PORTB
CK
Q
N TRIS Reg.
D Q
VSS
VSS
WR TRISB
CK
Q
RD TRISB ANSEL Reg. D
WR ANSEL
Q Q
CK
RD ANSEL IOCB Reg.
D Q
TTL
WR IOCB
CK
Q
Set RBIF
...
From other RB<7:0> pins
Q
D EN Q1
RD IOCB
Q D EN EN Q D EN Q3
RD PORTB
Analog Function Enable AN6
ANSEL<6> 0 0 1
TRISB<2> 1 0 x
FUNCTION Digital In Digital Out Analog In
PORTB<2> READ Pin Pin 0
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 39
PIC16C781/782
FIGURE 3-12:
CAL_ACTIVE OPAON
Data Bus
BLOCK DIAGRAM OF RB3/AN7/OPA PIN
WPUB Reg.
D Q
OPA Output
VDD
WR WPUB RD WPUB
CK
Q
RBPU
P Pull-up
Weak
PORTB Reg.
D Q
VDD P
VDD
RB3/AN7/OPA
WR PORTB
CK
Q
N TRIS Reg.
D Q
VSS
VSS
WR TRISB
CK
Q
RD TRISB ANSEL Reg. D WR ANSEL CK Q Q
TTL
RD ANSEL IOCB Reg.
D Q
WR IOCB RD IOCB
CK
Q
Set RBIF
...
From other RB<7:0> pins
Q D EN EN
Q
D EN
Q1
Q
D EN
RD PORTB Analog Function Enable AN7/OPA
Q3
OPA MODULE ANSEL<7> OPAON 0 0 1 1 CAL_ACTIVE x x 0 1 0 1 1 1 Digital Analog Analog Analog HI-Z Digital I/O Analog In OPA Output Calibration Pin 0 0 0 ADC/C1/C2 INPUT FUNCTION PORTB<3> READ
Analog HI-Z = No internal drive on pin (analog input) during calibration.
DS41171A-page 40
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
FIGURE 3-13:
Data Bus WR WPUB
BLOCK DIAGRAM OF RB4 PIN
WPUB Reg.
D Q
CK
Q RBPU
VDD P Weak
RD WPUB
Pull-up
PORTB Reg.
D Q
VDD
P
VDD RB4
WR PORTB
CK
Q
N
TRIS Reg.
D Q
VSS
VSS
WR TRISB
CK
Q
RD TRISB
TTL
RD IOCB
IOCB Reg.
D Q
WR IOCB
CK
Q
Set RBIF
...
From other RB<7:0> pins
Q D EN EN
Q
D EN Q1
Q
D EN
Q3
RD PORTB
TRISB<4> 0 1
FUNCTION Digital Out Digital In
PORTB<4> READ Pin Pin
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 41
PIC16C781/782
FIGURE 3-14:
Data Bus WR WPUB
BLOCK DIAGRAM OF RB5 PIN
WPUB Reg.
D Q
CK
Q RBPU
VDD P Weak Pull-up
RD WPUB
PORTB Reg.
D Q
VDD
P
VDD RB5
WR PORTB
CK
Q
N
TRIS Reg.
D Q
VSS
VSS
WR TRISB
CK
Q
RD TRISB
TTL
RD IOCB
IOCB Reg.
D Q
WR IOCB
CK
Q
Set RBIF
...
From other RB<7:0> pins
Q D EN EN
Q
D EN Q1
Q
D EN
RD PORTB
Q3
TRISB<5> 0 1
FUNCTION Digital Out Digital In
PORTB<5> READ Pin Pin
DS41171A-page 42
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
FIGURE 3-15: BLOCK DIAGRAM OF RB6/C1/PSMC1A PIN
C1OE SMCON PSMC1A C1OUT WPUB Reg. Data Bus WR WPUB RD WPUB Data Reg. D Q WR PORTB CK Q D CK Q Q
VDD
RBPU
P Weak Pull-up
VDD VDD P RB6/C1/PSMC1A
TRIS Reg.
D
WR TRISB
Q Q
N VSS VSS
CK
RD TRISB
TTL
RD PORTB RD IOCB IOCB Reg.
D WR IOCB CK
Q
Q
Serial Programming Clock
Q
D EN Q1
Set RBIF
From other RB<7:0> pins
Q
D
EN
RD Port Q3
PSMC SMCON x 0 0 1
COMPARATOR C1OE x 0 1 x
PORTB TRISB<6> 1 0 0 0
FUNCTION Digital In Digital Out C1OUT PSMC1A
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 43
PIC16C781/782
FIGURE 3-16: BLOCK DIAGRAM OF RB7/C2/PSMC1B/T1G PIN
C2OE SCEN SMCOM SMCON RD WPUB RBPU WPUB Reg. Data Bus D Q Q VSS VDD VDD P Weak Pull-up RB7/C2/PSMC1B/T1G
WR WPUB
CK
Data Reg. D WR PORTB Q Q
CK
TRIS Reg. D WR TRISB Q Q C2OUT VDD CK P
PSMC1B N RD TRISB SC Switch RD IOCB VSS
TTL
RD PORTB IOCB Reg.
D Q
WR IOCB Serial Programming Data and Timer1 Gate
CK
Q
Q
D Q1
Set RBIF
EN
Q From other RB<7:0> pins
D RD Port Q3
EN
PSMC MODULE SMCON x 0 1 0 1 1 1 SMCOM x x 0 x 0 0 1 SCEN x x 0 x 0 1 x
COMPARATOR C2OE x 0 0 1 1 x x
PORTB TRISB<7> 1 0 0 0 0 0 0
FUNCTION Digital In Digital Out Digital Out C2OUT C2OUT Slope Compensation PSMC1B
DS41171A-page 44
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
TABLE 3-2:
Address 06h 86h 81h 95h 96h 9Dh
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 RB7 RBPU Bit 6 RB6 INTEDG Bit 5 RB5 T0CS Bit 4 RB4 T0SE Bit 3 Bit 2 Bit 1 Bit 0 RB3 PSA Value on: POR, BOR Value on all other RESETS
PORTB TRISB OPTION_REG WPUB IOCB
RB2 RB1 RB0 xxxx 0000 uuuu 0000 1111 1111 1111 1111 PS2 PS1 PS0 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1111 0000
PORTB Data Direction Register PORTB Weak Pull-up Control PORTB Interrupt-on-Change Control
ANSEL AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTB.
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Preliminary
DS41171A-page 45
PIC16C781/782
NOTES:
DS41171A-page 46
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
4.0 PROGRAM MEMORY READ (PMR)
3FFFh. When the device contains less memory than the full address range of the PMADRH:PMARDL registers, the Most Significant bits of the PMADRH register are ignored.
Program memory is readable during normal operation (full VDD range). It is read by indirect addressing through the following Special Function Registers: * * * * * PMCON1: Control PMDATH: Data High PMDATL: Data Low PMADRH: Address High PMADRL: Address Low
4.1
PMCON1 Register
PMCON1 is the control register for program memory accesses. Control bit RD initiates a read operation. This bit cannot be cleared, only set, in software. It is cleared in hardware at completion of the read operation.
When interfacing to the program memory block, the PMDATH and PMDATL registers form a 2-byte word, which holds the 14-bit data. The PMADRH and PMADRL registers form a 2-byte word, which holds the 12-bit address of the program memory location being accessed. Mid-range devices have up to 8K words of program EPROM with an address range from 0h to
4.2
PMDATH and PMDATL Registers
The PMDATH:PMDATL registers are loaded with the contents of program memory addressed by the PMADRH and PMADRL registers upon completion of a Program Memory Read command.
REGISTER 4-1:
PROGRAM MEMORY READ CONTROL REGISTER 1 (PMCON1: 18Ch)
R-1 Reserved bit7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/S-0 RD bit0
bit 7 bit 6-1 bit 0
Reserved: Read as `1' Unimplemented: Read as '0 RD: Read Control bit 1 = Initiates a Program memory read (read takes 2 cycles, RD is cleared in hardware) 0 = Reserved Legend: S = Settable bit R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
REGISTER 4-2:
PROGRAM MEMORY DATA HIGH (PMDATH: 10Eh)
U-0 -- bit7 U-0 -- R/W-0 PMD13 R/W-0 PMD12 R/W-0 PMD11 R/W-0 PMD10 R/W-0 PMD9 R/W-0 PMD8 bit0
bit 7-6 bit 5-0
Unimplemented: Read as '0 PMD<13:8>: Program Memory Data bits The value of the program memory word pointed to by PMADRH and PMADRL after a program memory read command. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 47
PIC16C781/782
REGISTER 4-3: PROGRAM MEMORY DATA LOW (PMDATL: 10Ch)
R/W-0 PMD7 bit7 bit 7-0 R/W-0 PMD6 R/W-0 PMD5 R/W-0 PMD4 R/W-0 PMD3 R/W-0 PMD2 R/W-0 PMD1 R/W-0 PMD0 bit0
PMD<7:0>: Program Memory Data bits The value of the program memory word pointed to by PMADRH and PMADRL after a program memory read command. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
REGISTER 4-4:
PROGRAM MEMORY ADDRESS HIGH (PMADRH: 10Fh)
U-0 -- bit7 U-0 -- U-0 -- R/W-x Reserved R/W-x Reserved R/W-x PMA10 R/W-x PMA9 R/W-x PMA8 bit0
bit 7-5 bit 4-3 bit 2-0
Unimplemented: Read as '0' Reserved: Read state is not guaranteed PMA<10:8>: PMR Address bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
REGISTER 4-5:
PROGRAM MEMORY ADDRESS LOW (PMADRL: 10Dh)
R/W-x PMA7 bit7 R/W-x PMA6 R/W-x PMA5 R/W-x PMA4 R/W-x PMA3 R/W-x PMA2 R/W-x PMA1 R/W-x PMA0 bit0
bit 7-0
PMA<7:0>: PMR Address bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
DS41171A-page 48
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
4.3 Reading the EPROM Program Memory
in the following instructions. PMDATH and PMDATL registers hold this value until another read or until RESET.
To read a program memory location, the user must write 2 bytes of the address to the PMADRH and PMADRL registers, then set control bit RD (PMCON1<0>). Once the read control bit is set, the Program Memory Read (PMR) controller uses the second instruction cycle after to read the data. This causes the second instruction immediately following the "BSF PMCON1,RD" instruction to be ignored. The data is available, in the very next cycle, in the PMDATH and PMDATL registers. Therefore, it can be read as 2 bytes
Note 1: Interrupts must be disabled during the time from setting PMCON1<0> (RD) to the second instruction thereafter. 2: The following instructions should not be used following the start of a PMR read cycle: CALL, GOTO, BTFSS, BTFSC, RETFIE, RETURN, SLEEP.
EXAMPLE 4-1:
OTP PROGRAM MEMORY READ
;* This code block will read 1 word of program ;* memory at the memory address: ;* PROG_ADDR_HI : PROG_ADDR_LO ;* data will be returned in the variables; ;* PROG_DATA_HI, PROG_DATA_LO
BANKSEL MOVLW MOVWF MOVLW MOVWF BANKSEL CLEAR GIE BCF BSF NOP NOP BSF MOVF MOVWF MOVF MOVWF
PMADRL PROG_ADDR_LO PMADRL PROG_ADDR_HI PMADRH PMCON1 INTCON, GIE PMCON1,RD
; Select Bank 2 ; ; Store LSB of address ; ; Store MSB of address ; Select Bank 3 ; ; ; ; ; ; Turn off INTs Initiate read Executed (Fig 4-1) Ignored (Fig 4-1) Turn on INTs Get LSB of word
INTCON, GIE PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI
; Get MSB of word
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 49
PIC16C781/782
4.4 Program Memory Read With Code Protect Set
When the device is code protected, the CPU can still perform the program memory read function.
TABLE 4-1:
Address 10Ch 10Dh 10Eh 10Fh 18Ch Name PMDATL
SUMMARY OF REGISTERS ASSOCIATED WITH PMR
Bit 7 PMD7 PMA7 -- -- Reserved Bit 6 PMD6 PMA6 -- -- -- Bit 5 PMD5 PMA5 PMD13 -- -- Bit 4 PMD4 PMA4 PMD12 -- Bit 3 PMD3 PMA3 PMD11 -- Bit 2 PMD2 PMA2 PMD10 PMA10 -- Bit 1 PMD1 PMA1 PMD9 PMA9 -- Bit 0 Value on: POR, BOR Value on all other RESETS
PMD0 0000 0000 0000 0000 PMA0 xxxx xxxx uuuu uuuu PMD8 --00 0000 --00 0000 PMA8 ---x xxxx ---u uuuu RD 1--- ---0 1--- ---0
PMADRL PMDATH PMADRH PMCON1
Reserved Reserved
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PMR.
FIGURE 4-1:
PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Program Memory ADDR
PC
PC+1
PMADRH,PMADRL
PC+3 PC+3
PC+4
PC+5
INSTR(PC-1) Executed here
BSF PMCON1,RD Executed here
INSTR(PC+1) Executed here
Forced NOP Executed here
INSTR(PC+3) Executed here
INSTR(PC+4) Executed here
RD bit
PMDATH PMDATL Register
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5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable Internal or external clock select Edge select for external clock 8-bit software programmable prescaler Interrupt on overflow from FFh to 00h When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal system clock. Also, there is a delay in the actual incrementing of Timer0 after synchronization. Additional information on external clock requirements is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
EXAMPLE 5-1:
INITIALIZING TIMER0
Figure 5-1 is a simplified block diagram of the Timer0 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
5.1
Timer0 Operation
;* This code block will configure Timer0 ;* for Polling, internal clock & 1:16 ;* prescaler ;* ;* Wait for TMR0 overflow code included BANKSEL TMR0 ; Select Bank 0 CLRF TMR0 ; Clear Timer0 ; Register BANKSEL MOVLW MOVWF OPTION_REG B'11000011' OPTION_REG ; Select Bank 1
Timer0 can operate as either a timer or a counter. Programming Timer0 is via the OPTION register (see Register 2-2). Timer0 mode is selected by clearing/setting the bit T0CS (OPTION_REG<5>). In Timer mode (T0CS = 0), the Timer0 module increments every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 increments either on every rising, or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge, setting selects the falling edge. Restrictions on the external clock input are discussed below.
; INT on L2H ; Internal clk, ; pscaler 1:16 ******************************************** ;* Wait for TMR0 overflow ;* T0_OVFL_WAIT TBFSS INTCON,T0IF ; Check for TMR0 ; overflow GOTO T0_OVFL_WAIT ; If clear, test ; again BCF INTCON,T0IF ; Clear interrupt
FIGURE 5-1:
TIMER0 BLOCK DIAGRAM
Data Bus
FOSC/4
0 1 1 Programmable Prescaler
PSOUT
8
RA4/T0CKI pin T0SE
0
Sync with Internal Clocks
PSOUT
TMR0
(2 TCY Delay) Set Interrupt Flag bit T0IF on Overflow
3 PS<2:0> T0CS Note 1: T0CS, T0SE, PSA, PS<2:0> (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram). PSA
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5.2 Prescaler
5.2.1
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 5-2). For simplicity, this counter is referred to as "prescaler" throughout this data sheet. Note: There is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control, i.e., it can be changed "on-the-fly" during program execution. Note: To avoid an unintended device RESET, a specific instruction sequence (shown in the PICmicroTM Mid-Range Reference Manual, DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
The prescaler is not readable or writable. The PSA and PS<2:0> bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. Clearing bit PSA assigns the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Setting bit PSA assigns the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction clears the prescaler along with the WDT. Note: Writing to TMR0 when the prescaler is assigned to Timer0 clears the prescaler count, but does not change the prescaler assignment.
5.3
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP.
5.4
Effects of RESET
A device RESET will program Timer0 for an external clock input on RA4/T0CKI, Hi-Low edge, and no prescaler. The TMR0 register is not cleared.
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FIGURE 5-2:
FOSC/4
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 1 0 T0SE T0CS PSA Sync with Internal Clocks (2 TCY Delay)
0 RA4/T0CKI pin
TMR0 reg
Set Interrupt Flag bit T0IF on Overflow
0 Watchdog Timer 1
8-bit Prescaler 8
8 - to - 1 MUX PSA
PS<2:0>
WDT Enable bit
0
1
PSA
WDT Time-out
Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION_REG<5:0>).
TABLE 5-1:
Address 01h,101h 0Bh,8Bh, 10Bh,18Bh 81h,181h
REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR
xxxx xxxx
Value on all other RESETS
uuuu uuuu 0000 000u 1111 1111
TMR0 INTCON OPTION_REG
Timer0 Register GIE RBPU ADIF INTEDG T0IE T0CS INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0
0000 000x 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Timer0.
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NOTES:
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6.0 TIMER1 MODULE WITH GATE CONTROL
EXAMPLE 6-1:
;* ;* ;* ;* ;* ;*
TIMER1 INITIALIZATION
The Timer1 module timer/counter has the following features: * 16-bit timer/counter (two 8-bit registers:TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt on overflow from FFFFh to 0000h * External enable input (T1G pin with TMR1GE bit = 1) * Option for Timer1 to use LP oscillator if device is configured to use INTRC w/o CLKOUT Timer1 Control register (T1CON) is shown in Register 6-1. Figure 6-2 is a simplified block diagram of the Timer1 module.
This code block will configure Timer1 for Polling, Ext gate of int clk (Fosc/4), & 1:1 prescaler. Wait for TMR1 overflow code included BANKSEL CLRF CLRF MOVLW MOVWF BSF TMR1L TMR1L TMR1H B'01000000' T1CON T1CON,TMR1ON ; ; ; ; ; ; Select Bank 0 Clear TMR1 LSB Clear TMR1 MSB Gate, Ps 1:1 Int clk Enable timer
;******************************************** ;* Wait for TMR1 overflow T1_OVFL_WAIT BANKSEL PIR1 T1_WAIT TBFSS PIR1,TMR1IF GOTO T1_WAIT BCF PIR1,TMR1IF
6.1
1. 2. 3.
Timer1 Operation
16-bit timer with prescaler. 16-bit synchronous counter. 16-bit asynchronous counter.
Timer1 can operate in one of three modes:
; Select Bank 0 ; ; Overflow? ; If 0, again ; Clear flag
In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI (RA6/ OSC2/CLKOUT/T1CKI). In addition, the Counter mode clock can be synchronized to the microcontroller clock or run asynchronously. In Counter and Timer modes, the counter/timer clock can be gated by the T1G input. If an external clock oscillator is needed (and the microcontroller is using INTRC w/o CLKOUT), Timer1 can use the LP oscillator as a clock source. Note 1: In Counter mode, the counter increments on the rising edge of the clock.
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6.2 Control Register T1CON
Control and configuration of Timer1 is by means of the T1CON register shown in Register 6-1. Timer1 is enabled by setting the TMR1ON bit (T1CON<0>). Clearing TMR1ON stops the timer, but does not clear the Timer1 register. The TMR1CS bit (T1CON<1>) determines the Timer mode. When TMR1CS is set, the timer is configured as a counter and receives its clock from RA6/OSC2/ CLKOUT/T1CKI. When cleared, the timer is configured as a timer and its clock is derived from FOSC/4. The T1SYNC bit (T1CON<2>) determines Timer1's synchronization. If cleared, the timer clock is synchronized to the system clock. If set, the timer is asynchronous. The Timer1 clock gate function is enabled by setting the TMR1GE bit (T1CON<6>). When TMR1GE is set, the T1G input will control the clock input to the timer/ counter. A low on the T1G input will cause Timer1 to increment at the clock rate, a high will hold the timer at its present value. The T1OSCEN bit (T1CON<3>) enables the LP oscillator as a clock source for Timer1. This mode is a replacement for the regular external oscillator. T1CKPS<1:0> determines the prescaler value for the timer. Available prescaler values are: T1CKPS<1:0> Prescaler Value Bit 1 1 1 0 0 Note: Bit 0 1 0 1 0 1:8 1:4 1:2 1:1
To use the LP oscillator as the Timer1 oscillator: 1. TMR1CS must be set. 2. T1OSCEN must be set. 3. The Configuration Word must select INTRC w/o CLKOUT.
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REGISTER 6-1: TIMER1 CONTROL REGISTER (T1CON: ADDRESS 10h)
U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as '0' TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if T1G pin is low 0 = Timer1 is on T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: LP Oscillator Enable Control bit If INTRC w/o CLKOUT is selected in the configuration word, oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RA6/OSC2/CLKOUT/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 T1OSCEN R/W-0 R/W-0 R/W-0 bit 0 TMR1GE T1CKPS1 T1CKPS0 T1SYNC TMR1CS TMR1ON
bit 5-4
bit 3
bit 2
bit 1
bit 0
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FIGURE 6-1:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled
Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
FIGURE 6-2:
TIMER1 ON THE PIC16C781/782 BLOCK DIAGRAM
TMR1ON TMR1GE TMR1ON TMR1GE To C2 Comparator Module TMR1 Clock TMR1 0 TMR1H TMR1L 1 RA7/OSC1/CLKIN LP OSCILLATOR T1SYNC Synchronized Clock Input
RB7/C2/ PSMC1B/T1G
Set Flag bit TMR1IF on Overflow
1
FOSC/4 Internal Clock Prescaler 1, 2, 4, 8
Synchronize det SLEEP Input
RA6/OSC2/ CLKOUT/ T1CKI INTRC w/o CLKOUT Mode T1OSCEN LPEN
0
2
T1CKPS<1:0> TMR1CS
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6.3 Timer1 Oscillator for the PIC16C781/782 6.4 Timer1 Interrupt
The TMR1 register pair (TMR1H and TMR1L) increments from 0000h to FFFFh and then rolls over to 0000h. When Timer1 rolls over, the TMR1IF bit (PIR1<0>) is set. To enable an interrupt, the TMR1IE bit (PIE1<0>), the GIE (INTCON<7>) and the PEIE bit (INTCON<6>) must be set prior to rollover. To clear the interrupt, the TMR1IF must be cleared by software prior to re-enabling interrupts.
When the microcontroller is using INTRC w/o CLKOUT, Timer1 can enable and use the LP oscillator as the Timer1 oscillator. When enabled, Timer1 oscillator operation is solely controlled by the T1OSCEN bit. The oscillator will operate independently of the TMR1ON bit, allowing the programmer to start and stop the Timer/Counter using the TMR1ON bit. The oscillator will also operate during SLEEP, allowing continuous timekeeping with Timer1. The electrical requirements for the LP oscillator, when used as the Timer1 oscillator, are the same as when the oscillator is used in LP mode. Note: The oscillator requires a startup and stabilization time before use. Therefore, T1OSCEN should be set, and a suitable delay observed, prior to enabling Timer1 (see Section 14.2).
Note:
When enabling the Timer1 interrupt, the user should clear both TMR1 registers and the TMR1IF prior to enabling interrupts.
6.5
Effects of RESET
Only POR and BOR Resets clear T1CON, disabling Timer1. All other RESETS do not affect Timer1.
TABLE 6-1:
Address 0Bh 0Ch 8Ch 0Eh 0Fh 10h Name INTCON PIR1 PIE1 TMR1L TMR1H T1CON
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 7 GIE LVDIF LVDIE Bit 6 PEIE ADIF ADIE Bit 5 T0IE C2IF C2IE Bit 4 INTE C1IF C1IE Bit 3 RBIE -- -- Bit 2 T0IF -- -- Bit 1 INTF -- -- Bit 0 RBIF TMRIF TMRIE Value on: POR, BOR Value on all other RESETS
0000 000X 0000 000u 0000 ---0 0000 ---0 0000 ---0 0000 ---0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Least Significant Byte of the 16-bit TMR1 Register Most Significant Byte of the 16-bit TMR1 Register --
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Timer1.
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7.0 VOLTAGE REFERENCE MODULE (VR)
Setting the VREN flag (REFCON<3>), enables the module. Following initial start-up, the module should be allowed to stabilize for best accuracy. See Section 17.0 for information concerning stabilization times and conditions. To route the reference voltage to the external RB0/INT/ AN4/VR pin, the VROE flag (REFCON<2>) must be set.
The Voltage Reference module provides an on-chip nominal 3.072V reference voltage for the following: * ADC converter * DAC converter * VR output on the RB0/INT/AN4/VR pin The source for the reference voltage comes from a bandgap reference. The control register for this module is the REFCON register shown in Register 7-1. Note 1: If the VR module is to be used by the DAC, ADC, or VR output:, the VR module must be enabled using VREN (REFCON<3>). 2: When VREN = 1 and VROE = 1, the output driver for RB0/INT/AN4/VR will be driven tri-state and the analog driver for the VR output will be enabled. A read of RB0 will return a `0'.
7.1
Effects of RESET
A device RESET clears the REFCON register, disabling the voltage reference.
7.2
Registers Associated with VR
A summary of the registers associated with VR is shown in Table 7-1.
REGISTER 7-1:
VOLTAGE REFERENCE CONTROL REGISTER (REFCON: 9Bh)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R/W-0 VREN R/W-0 VROE U-0 -- U-0 -- bit 0
bit 7-4 bit 3
Unimplemented: Read as `0' VREN: Voltage Reference Enable bit (VR = 3.072V nominal) 1 = VR reference is enabled 0 = VR reference is disabled VROE: Voltage Reference Output Enable bit If VREN = 1: 1 = Enabled, VR voltage reference is output on RB0 0 = Voltage reference is not available externally If VREN = 0: This bit is ignored Unimplemented: Read as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 2
bit 1-0
TABLE 7-1:
Address 09Bh
SUMMARY OF REGISTERS ASSOCIATED WITH VR
Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 VREN Bit 2 VROE Bit 1 -- Bit 0 -- Value on: POR, BOR Value on all other RESETS
Name REFCON
---- 00-- ---- 00--
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8.0 PROGRAMMABLE LOW VOLTAGE DETECT MODULE (PLVD)
condition. The time between TA and TB is then available to the microcontroller for completing a `graceful' powerdown before VDD falls below VB. Figure 8-2 is a simplified block diagram for the PLVD module, showing the VDD resistor ladder, control register, and voltage comparator.
The PLVD module monitors the VDD power supply of the microcontroller and signals the microcontroller whenever VDD drops below its trip voltage. The signal acts as an `early warning' of power-down, allowing the microcontroller to finish any critical `housekeeping' tasks prior to completing power-down. Figure 8-1 demonstrates a potential application of the PLVD module (typical battery operation). At time TA, the VDD supply voltage (VA) has fallen below the PLVD reference voltage. The PLVD voltage comparator then sets the LVDIF bit (PIR<7>), indicating a low voltage
Note:
For low power applications, current drain can be minimized by enabling the module only during regular polled testing. When not in use, the module is disabled by clearing the LVDEN bit (LVDCON<4>), which also powers down the resistor ladder between VDD and Vss.
FIGURE 8-1:
TYPICAL LOW VOLTAGE DETECT APPLICATION
VA VB Voltage Legend: VA = PLVD trip point VB = Minimum valid device operating voltage
Time
TA
TB
8.1
Control Register
The PLVD module is controlled via the LVDCON register shown in Register 8-1. To enable the module for testing, the LVDEN bit (LVDCON<4>) must be set. This will enable the onboard voltage reference and connect the resistor ladder between VDD and Vss. Clearing LVDEN will disable the module and disconnect the resistor ladder from Vss.
The trip voltage is set by programming the LVDL<3:0> bit (LVDCON<3.0>). The voltages available are listed in Register 8-1. Note that voltages below 2.5V and above 4.75V are not available and should not be used. The BGST bit (LVDCON<5>) is a status bit indicating that the internal reference voltage bandgap has stabilized. No test should be performed until this bit is set. The low voltage output flag for the PLVD module is the LVDIF bit (PIR1<6>).
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8.2 Operation
The PLVD indicates a low voltage condition by setting the LVDIF bit in the PIR1 register. Once set by the PLVD module, the LVDIF bit will remain set until cleared by software. For proper indication of a low voltage condition, the user should clear this bit prior to testing. To test for a low voltage condition, the PLVD module compares the divided output of VDD against an internal bandgap reference. The PLVD module automatically enables this reference whenever it is enabled and provides a stability bit, BGST, to indicate when it has stabilized. The bandgap reference is also enabled by other modules within the PIC16C781/782 as part of their operation. Other modules using the bandgap include the following: * VR module * BOR module * OPA calibration module
FIGURE 8-2:
LOW VOLTAGE DETECT BLOCK DIAGRAM
VDD PLVD Control Register
16 to 1 MUX
LVDIF
LVDEN
Internally Generated Reference Voltage
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If another module has enabled the bandgap, then the reference will be stable when the PLVD module is enabled and the BGST flag can be ignored. However, if the bandgap has not been previously enabled, the LVDIF bit will not be valid until the BGST bit is set (see Figure 8-3). Systems using the PLVD interrupt should not enable the interrupt until after the reference is stable to prevent spurious interrupts. 2. 3. 4. 5. Ensure that PLVD interrupts are disabled (the LVDIE bit is cleared, or the GIE bit is cleared). Enable the PLVD module (set the LVDEN bit in the LVDCON register). Wait for the PLVD module to stabilize (the BGST bit to become set). Clear the PLVD interrupt flag, which may have falsely become set until the PLVD module has stabilized (clear the LVDIF bit). Enable the PLVD interrupt (set the LVDIE and the GIE bits).
8.2.1
SETTING UP THE PLVD MODULE
6.
The following steps are needed to set up the PLVD Module: 1. Write the value to the LV3:LV0 bits (LVDCON register), which selects the desired PLVD Trip Point.
FIGURE 8-3:
CASE 1:
LOW VOLTAGE DETECT WAVEFORMS
LVDIF may not be set
VDD
. VLVD
LVDIF Enable LVD Internally Generated Reference Stable LVDIF cleared in software
CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable LVDIF cleared in software Attempt to clear LVDIF in software but remains set as LVD condition still exists
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REGISTER 8-1: PROGRAMMABLE LOW VOLTAGE DETECT REGISTER (LVDCON: 9Ch)
U-0 -- bit 7 bit 7-6 bit 5 Unimplemented: Read as '0' BGST: Internal Reference Voltage Stable Flag bit 1 = Reference is stable 0 = Reference is not stable LVDEN: Low Voltage Detect Power Enable bit 1 = Enables PLVD, powers up LVD circuit 0 = Disables PLVD, powers down LVD circuit. LV<3:0>: Low Voltage Detection Limit bits 1111 = Reserved 1110 = 4.5V typical 1101 = 4.2V typical 1100 = 4.0V typical 1011 = 3.8V typical 1010 = 3.6V typical 1001 = 3.5V typical 1000 = 3.3V typical 0111 = 3.0V typical 0110 = 2.8V typical 0101 = 2.7V typical 0100 = 2.5V typical 0011 = Below valid operating voltage 0010 = Below valid operating voltage 0001 = Below valid operating voltage 0000 = Below valid operating voltage Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R-0 BGST R/W-0 LVDEN R/W-0 LV3 R/W-1 LV2 R/W-0 LV1 R/W-1 LV0 bit 0
bit 4
bit 3-0
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Example 8-1 shows the configuration of the PLVD module and a sample polling routine to monitor for low voltage conditions.
EXAMPLE 8-1:
PLVD EXAMPLE
;************************************************ ;* This code block will configure the PLVD for polling ;* and set the trip point for 4.2 to 4.4 volts ;* Includes polling routine ;* BANKSEL BCF MOVLW MOVWF WRM_UP BTFSS GOTO BANKSEL BCF LVDCON PIE1,LVDIE B'00011101' LVDCON ; Select Bank 1 ; Disable PLVD interrupt ; Enable PLVD, 4.2-4.4V trip
LVDCON,BGST WRM_UP PIR1 PIR1,LVDIF
; ; ; Select Bank 0 ; Clear PLVD interrupt flag
;************************************************** ;* Test for PLVD trip BANKSEL BTFSC GOTO PIR1 PIR1,LVDIF LO_V_DET ; Select Bank 0 ; Test for PLVD trip ; If tripped save 4 pwrfail
8.3
Operation During SLEEP
8.4
Effects of a RESET
When enabled, the PLVD circuitry continues to operate during SLEEP. If the device voltage crosses the trip point, the LVDIF bit is set and the device awakens from SLEEP. Device execution continues from the interrupt vector address, if interrupts have been globally enabled.
A device RESET forces all registers to their RESET state. This forces the PLVD module to be disabled.
8.5
Low Voltage Detect Registers
The registers associated with Programmable Low Voltage Detect are shown in Table 8-1.
TABLE 8-1:
Address 09Ch 08Ch 08Ch Name
SUMMARY OF REGISTERS ASSOCIATED WITH LOW VOLTAGE DETECT
Bit 7 -- LVDIE LVDIF Bit 6 -- ADIE ADIF Bit 5 BGST C2IE C2IF Bit 4 LVDEN C2IE C2IF Bit 3 LV3 -- -- Bit 2 LV2 -- -- Bit 1 LV1 -- -- Bit 0 LV0 TMR1IE TMR1IF Value on: POR, BOR
--00 0101 0000 ---0 0000 ---0
Value on all other RESETS
--00 0101 0000 ---0 0000 ---0
LVDCON PIE1 PIR1
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9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE
tures a snapshot of the voltage and holds it for the ADC. The ADC then generates the 8-bit result via successive approximation. The analog reference voltage (ADCREF) is software selectable from the following options: * * * * The analog positive supply: AVDD The reference input for Comparator C1: VREF1 The Voltage Reference module output: VR The DAC Converter module output: VDAC
The 8-bit ADC module, shown in Figure 9-1, has 10 inputs in the PIC16C781/782: * 8 external channels, AN<7:0> (RA<3:0> and RB<3:0>) * 2 internal channels, VR and VDAC The ADC allows conversion of an analog input signal to a corresponding 8-bit digital value. The desired channel is connected to a Sample-and-Hold by the input multiplexers. The output of the Sample-and-Hold cap-
The ADC has the unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the ADC conversion clock must be derived from the ADC's dedicated internal RC oscillator.
FIGURE 9-1:
ADC MODULE BLOCK DIAGRAM
VOLTAGE COMPARATOR MODULE
OPA MODULE 4 RA0/AN0/OPA+ RA1/AN1/OPARA2/AN2/VREF2 RA3/AN3/VREF1 RB0/INT/AN4/VR RB1/AN5/VDAC RB2/AN6 RB3/AN7/OPA 0 1 2 3 4 5 6 7 8 9 DAC MODULE ADON GO/DONE AVDD VREF1 VR VDAC 0 1 2 3 Sample and Hold ADCREF ADC 8 ADRES CHS<3:0> VCFG<1:0>
VR MODULE
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 69
PIC16C781/782
9.1 Control Registers
9.1.1 ADCON0 REGISTER
The ADC module has three registers. These registers are: * ADC Result Register: * ADC Control Register 0: * ADC Control Register 1: ADRES ADCON0 ADCON1 The ADCON0 register, shown in Register 9-1, controls the following: * * * * Clock source and prescaler Input channel Conversion start/stop Enabling of the ADC module
The ADCON0 register, shown in Register 9-1, controls the operations and input channel selection for the ADC module. The ADCON1 register, shown in Register 9-3, selects the voltage reference used by the ADC module. The ADRES register, shown in Register 9-2, holds the 8-bit result of the conversion. Additional information on using the ADC module can be found in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023) and in Application Note AN546 (DS00546).
Setting the ADON bit, ADCON0<0>, enables the ADC module. Clearing ADON disables the module and terminates any conversion in process. The ADCS<1:0> bits (ADCON0<7:6>) determine the clock source used by the ADC module. The CHS<3:0> bits (ADCON0<5:3,1>) determine the input channel to the ADC module. CHS<3> specifically determines whether the source is internal or external. Setting the GO/DONE bit (ADCON0<2>) initiates the conversion process. The ADC clears this bit at the completion of the conversion process.
REGISTER 9-1:
ADC CONTROL REGISTER 0 (ADCON0: 1Fh)
R/W-0 ADCS1 bit 7 R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/S-0 GO/DONE R/W-0 CHS3 R/W-0 ADON bit 0
bit 7-6
ADCS<1:0>: ADC Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = ADRC (clock derived from a dedicated RC oscillator) CHS<2:0>: Analog Channel Select bits (select which channel to convert) If CHS3 = 0: If CHS3 = 1: 000 = channel 0 (AN0) 000 = VR 001 = channel 1 (AN1) 001 = VDAC 010 = channel 2 (AN2) 010 = Reserved. Do not use. 011 = channel 3 (AN3) 011 = Reserved. Do not use. 100 = channel 4 (AN4) 100 = Reserved. Do not use. 101 = channel 5 (AN5) 101 = Reserved. Do not use. 110 = channel 6 (AN6) 110 = Reserved. Do not use. 111 = channel 7 (AN7) 111 = Reserved. Do not use. GO/DONE: ADC Conversion Status bit 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. 0 = ADC conversion is not in progress (this bit is cleared by hardware when conversion is complete) CHS3: Analog Channel Select bit 1 = Internal channel selected for conversion 0 = External channel selected for conversion ADON: ADC On bit 1 = ADC enabled 0 = ADC disabled Legend: S = Settable bit R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 5-3
bit 2
bit 1
bit 0
DS41171A-page 70
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
9.1.2 ADCON1 REGISTER 9.1.3 ADRES REGISTER
The ADCON1 register, shown in Register 9-3, controls the reference voltage selection for the ADC module. Bits VCFG<1:0> (ADCREF). select the reference voltage The ADRES register, shown in Register 9-2, contains the 8-bit result of the conversion. At the completion of the ADC conversion: * 8-bit result is loaded into ADRES. * GO/DONE bit (ADOCN0<2>) is cleared. * ADC interrupt flag bit ADIF (INTCON<6> and PIR1<6>) are set. * If the ADC interrupt is enabled, an interrupt is also generated.
REGISTER 9-2:
ADC RESULT REGISTER (ADRES: 1Eh)
R/W-x AD7 bit 7 R/W-x AD6 R/W-x AD5 R/W-x AD4 R/W-x AD3 R/W-x AD2 R/W-x AD1 R/W-x AD0 bit 0
bit 7-0
AD<7:0>: ADC Conversion Results bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
REGISTER 9-3:
ADC CONTROL REGISTER 1 (ADCON1: 9Fh)
U-0 -- bit 7 U-0 -- R/W-0 VCFG1 R/W-0 VCFG0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7-6 bit 5-4
Unimplemented: Read as '0' VCFG<1:0>: Voltage Reference Configuration bits 00 = AVDD 01 = VREF1 10 = VR 11 = VDAC Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 3-0
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 71
PIC16C781/782
9.2
9.2.1
Configuring the ADC Module
CONFIGURING ANALOG PORT PINS
9.2.2
CONFIGURING THE REFERENCE VOLTAGES
The ANSEL and TRISB registers control the operation of the ADC port pins. The port pins to be used as analog inputs must have their corresponding TRISB bits set (= 1). The proper ANSEL bits must also be set (analog input) to disable the digital input buffer.
The VCFG<5:4> bits in the ADCON1 register configure the ADC module reference voltage input, ADCREF. The reference input can come from any of the following: * * * * Internal voltage reference (VR) External comparator C1 reference (VREF1) DAC output (VDAC) Analog positive supply (AVDD)
Note 1: The ADC operation is independent of the state of the TRISB or ANSEL bits. These bits must be configured by the firmware prior to initiation of an ADC conversion. 2: When reading the PORTA or PORTB registers, all pins configured as analog input channels will read as a `0'. 3: Analog levels on any pin that is defined as a digital input, including AN<7:0>, may cause the input buffer to consume excess supply current.
If an external reference is chosen for the ADCREF input, the port pin that multiplexes with the incoming external reference must also be configured as an analog input.
9.2.3
SELECTING THE ADC CONVERSION CLOCK
The ADC conversion cycle requires 9.5TAD. The source of the ADC conversion clock is software selectable. The four possible options for ADC clock are: * * * * FOSC/2 FOSC/8 FOSC/32 ADRC (clock derived from a dedicated internal RC oscillator)
For correct ADC conversion, the ADC conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 sec. Table 9-1 shows the resultant TAD times derived from the device operating frequencies and the ADC clock source selected.
TABLE 9-1:
TAD vs. DEVICE OPERATING FREQUENCIES: PIC16C781/782
Device Frequency 20 MHz 100 ns(2) 400 ns 1.6 s 2 - 6 s(1,4) 5 MHz 400 ns(2) 1.6 s 6.4 s 2 - 6 s(1,4) 1.25 MHz 1.6 s 6.4 s 25.6 s(3) 2 - 6 s(1,4) 333.33kHz 6 s 24 s(3) 96 s(3) 2 - 6 s(1)
ADC Clock Source (TAD) Operation 2 TOSC 8 TOSC 32 TOSC RC Legend: Note 1: 2: 3: 4: ADCS1:ADCS0 00 01 10 11
Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When device frequency is greater than 1 MHz, the RC ADC conversion clock source is recommended for SLEEP operation only.
DS41171A-page 72
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
9.2.4 INITIATING A CONVERSION
The Analog-to-Digital conversion is initiated by setting the GO/DONE bit in ADCON0 register. When the conversion is complete, the ADC module: * Clears the GO/DONE bit * Sets the ADIF flag in the PIR1 register * Generates an interrupt if the ADIE, PEIE, and GIE bits are set. If the conversion must be aborted, the GO/DONE bit can be cleared in software. The ADRES register will not be updated with the partially completed ADC conversion sample. Instead, the ADRES will contain the value from the last completed conversion. After an aborted conversion, a 2TAD delay is required before another acquisition/conversion can be initiated. Following the delay, an input acquisition is automatically started on the selected channel. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the ADC. Example 9-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following system assumptions. CHOLD = 51.2 pF RS = 10k 1/2 LSb error RSS = 7k @ VDD = 5V Note 1: The reference voltage (ADCREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification. 4: After a conversion has completed, a 1.0TAD delay must be completed before acquisition can begin again. During this time the holding capacitor is not connected to the selected ADC input channel.
9.3
ADC Acquisition Requirements
For the ADC module to meet its specified accuracy, the internal Sample-and-Hold capacitor (CHOLD) must be allowed to charge to within 1/2 LSb of the voltage present on the input channel (see analog input model in Figure 9-2). The analog source resistance (RS) and the internal sampling switch resistance (RSS) will directly affect the time required to charge CHOLD. In addition, RSS will vary over the power supply voltage range (AVDD), and RS will affect the input offset voltage at the analog input (due to pin leakage current). Therefore: 1. 2. The maximum recommended impedance for any analog sources is 10 kOhms. Following any change in the analog input channel selection, a minimum acquisition delay must be observed before another conversion can begin (see Equation 9-1).
EXAMPLE 9-1:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ = Amplifier Setting Time + Holding Capacitor Charging Time + Temperature Coefficient TACQ = 5 s + TCAP + [(Temp - 25C)(0.05 s/C)] TCAP = -CHOLD (RIC + RSS + RS) In(1/511) -51.2 pF (1 k + 7k + 10k) In(0.0020) -51.2 pF (18 k) In(0.0020) -0.921 s (-6.2364) 5.747 s TACQ = 5 s + 5.747 s + [(50C -25C)(0.05s/C)] 10.747 s + 1.25 s 11.997 s
To calculate the minimum acquisition time, Equation 9-1 may be used. This equation calculates the acquisition time to within 1/2 LSb error, assuming an 8-bit conversion (512 steps for the PIC16C781/782 ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified accuracy.
EQUATION 9-1:
ADC MINIMUM CHARGING TIME
VHOLD = (ADCREF-(ADCREF/512))*(1-e-TCAP/CHOLD(RIC+Rss+Rs)) Given: VHOLD = (ADCREF/512), for 1/2LSb resolution The above equation reduces to: TCAP = -(51.2 pF)(1 k + RSS + RS) Ln(1/511)
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 73
PIC16C781/782
FIGURE 9-2: ANALOG INPUT MODEL
VDD VT = 0.6V
Sampling Switch RIC 1k SS
RSS
RS
ANx
VA
CPIN 5 pF
VT = 0.6V
ILEAKAGE 500 nA
CHOLD = DAC capacitance = 51.2 pF VSS
Legend: CPIN = input capacitance = threshold voltage VT ILEAKAGE = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC)
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch ( k )
9.4
ADC Configuration and Conversion
EXAMPLE 9-2:
ADC CONVERSION
Example 9-2 demonstrates an ADC conversion. The RA0/AN0 pin is configured as the analog input. The reference voltage selected is the device AVDD. The ADC interrupt is enabled, and the ADC conversion clock is ADRC. Clearing the GO/DONE bit during a conversion aborts the current conversion. The ADRES register is NOT updated with the partially completed ADC conversion sample. That is, the ADRES register continues to contain the value of the last completed conversion (or the last value written to the ADRES register). After the ADC conversion is aborted, a 2TAD wait period is required before the next acquisition is started. After this 2TAD wait period, an acquisition is automatically started on the selected channel.
;******************************************** ;* This code block will configure the ADC ;* for polling, AVDD as reference, RC clock ;* and RA0 input. ;* ;* Conversion start & wait for complete ;* polling code included. ;* ; Select Bank 1 BANKSEL ADCON1 CLRF ADCON1 ; AVDD as VREF BSF TRISA,0 ; Set RA0 as input BSF ANSEL,0 ; Set RA0 as analog
BANKSEL MOVLW MOVWF ADCON0 ; Select Bank0 B'11000001' ADCON0 ; RC, Ch 0, ADC on
;******************************************** ;* Start & Wait for ADC complete, assumes ;* minimum acquisition delay from ;* configuration. ADC_CNVRT BANKSEL BSF ADC_CN_LOOP BTFSC GOTO MOVF
ADCON0 ADCON0,GO
; Select Bank 0 ; Start convert
ADCON0,GO ; Test for end ADC_CN_LOOP ; If not, wait ADRES,W ; Get result
DS41171A-page 74
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
9.4.1 FASTER CONVERSION/LOWER RESOLUTION TRADE-OFF
9.6
ADC Accuracy/Error
Not all applications require a result having 8-bits of resolution. Some may instead, require a faster conversion time. The ADC module allows users to make a trade-off of conversion speed for resolution. Regardless of the resolution required, the acquisition time is the same. To speed up the conversion, the clock source of the ADC module may be switched during the conversion, so that the TAD time violates the minimum specified time (see the applicable Electrical Specification). Once the switch is made, all the following ADC result bits are invalid (see ADC Conversion Timing in the Electrical Specifications section). The clock source may only be switched between the three oscillator options (it cannot be switched from/to RC). The equation to determine the time before the oscillator must be switched for a desired resolution is as follows: Conversion time = 2TAD + N * TAD + (8 - N)(2TOSC) Where: N = number of bits of resolution required. Since the TAD is based on the device oscillator, the user must employ some method (such as a timer, software loop, etc.) to determine when the ADC oscillator must be changed.
The absolute accuracy (absolute error) specified for the ADC converter includes the sum of all contributions for: * * * * * * Offset error Gain error Quantization error Integral non-linearity error Differential non-linearity error Monotonicity
The absolute error is defined as the maximum deviation from an actual transition versus an ideal transition for any code. The absolute error of the ADC converter is specified as < 1 LSb for ADCREF = VDD (over the device's specified operating range). However, the accuracy of the ADC converter degrades as VDD diverges from VREF. For a given range of analog inputs, the output digital code will be the same. This is due to the quantization of the analog input to a digital code. Quantization error is typically 1/2 LSb and is inherent in the analog to digital conversion process. The only way to reduce quantization error is to use an ADC with greater resolution of the ADC converter. Offset error measures the first actual transition of a code versus the first ideal transition of a code. Offset error shifts the entire transfer function. Offset error can be calibrated out of a system, or introduced into a system, through the interaction of the total leakage current and source impedance at the analog input. Gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error. This error appears as a change in slope of the transfer function. The difference in gain error to full scale error is that full scale does not take offset error into account. Gain error can be calibrated out in software. Linearity error refers to the uniformity of the code changes. Linearity errors cannot be calibrated out of the system. Integral non-linearity error measures the actual code transition versus the ideal code transition, adjusted by the gain error for each code. Differential non-linearity measures the maximum actual code width versus the ideal code width. This measure is unadjusted. If the linearity errors are very large, the ADC may become non-monotonic. This occurs when the digital values for one or more input voltages are less than the value for a lower input voltage.
9.5
ADC Operation During SLEEP
The ADC module can operate during SLEEP mode. This requires that the ADC clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the ADC module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed the GO/DONE bit is cleared, and the result is loaded into the ADRES register. If the ADC interrupt is enabled, the device awakens from SLEEP. If the ADC interrupt is not enabled, the ADC module is turned off, although the ADON bit remains set. When the ADC clock source is another clock option (not RC), a SLEEP instruction causes the present conversion to be aborted and the ADC module to be turned off. The ADON bit remains set. Turning off the ADC places the ADC module in its lowest current consumption state. Note: For the ADC module to operate in SLEEP, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an ADC conversion in SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE bit.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 75
PIC16C781/782
9.6.1 CLOCK NOISE
9.9
Transfer Function
In systems where the device frequency is low, use of the ADC RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator. TAD must not violate the minimum and should be 8 s for preferred operation. This is because TAD, when derived from TOSC, is kept away from on-chip phase clock transitions. This reduces, to a large extent, the effects of digital switching noise. This is not possible with the RC derived clock. The loss of accuracy due to digital switching noise can be significant if many I/O pins are active. In systems where the device enters SLEEP mode after the start of the ADC conversion, the RC clock source selection is required. In this mode, the digital noise from the modules in SLEEP is stopped. This method gives high accuracy.
The ideal transfer function of the ADC converter is as follows: the first transition occurs when the analog input voltage (VAIN) is Analog ADCREF/256 (Figure 9-3).
9.10
References
A good reference for ADC converters is the "AnalogDigital Conversion Handbook" third edition, published by Prentice Hall (ISBN 0-13-03-2848-0).
FIGURE 9-3:
ADC TRANSFER FUNCTION
9.7
Effects of a RESET
Digital Code Output
FFh FEh
A device RESET forces all registers to their RESET state. This forces the ADC module to be turned off, and any conversion is aborted. The value that is in the ADRES register is not modified for a Power-on Reset. The ADRES register contains unknown data after a Power-on Reset.
04h 03h 02h 01h 00h 256 LSb (Full Scale) 255 LSb 0.5 LSb 1 LSb 2 LSb 3 LSb
4 LSb
9.8
Connection Considerations
If the input voltage exceeds the rail values (VSS or VDD) by greater than 0.2V, then the accuracy of the conversion is out of specification. Note: Care must be taken when using the RB2/ AN6 pin in ADC conversions due to its proximity to the OSC1 pin.
Analog Input Voltage
An external RC filter is sometimes added for antialiasing of the input signal. The R component should be selected to ensure that the total source impedance is kept under the 10 k recommended specification. Any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin.
DS41171A-page 76
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
FIGURE 9-4: FLOW CHART OF ADC OPERATION
ADON = 0
Yes ADON = 0?
No
Acquire Selected Channel
Yes GO = 0?
No
ADC Clock = RC?
No
Yes
Start of ADC Conversion Delayed 1 Instruction Cycle
SLEEP Yes Instruction ?
Finish Conversion GO = 0 ADIF = 1
No
Device in SLEEP? No
Yes
Abort Conversion GO = 0 ADIF = 0
Finish Conversion GO = 0 ADIF = 1
Wake-up Yes From SLEEP?
No
Wait 2TAD
Finish Conversion GO = 0 ADIF = 1
SLEEP Power-down A/D
Wait 2TAD
Stay in SLEEP Power-down ADC
Wait 2TAD
TABLE 9-2:
Address 0Bh 8Ch 0Ch 1Eh 1Fh 9Fh 05h 06h 9Dh Name
REGISTERS/BITS ASSOCIATED WITH ADC, PIC16C781/782
Bit 7 GIE LVDIE LVDIF Bit 6 PEIE
ADIE ADIF
Bit 5 T0IE
C2IE C2IF
Bit 4 INTE
C1IE C1IF
Bit 3 RBIE -- -- CHS0 -- RA3 RB3
Bit 2 T0IF -- -- GO/DONE -- RA2 RB2
Bit 1 INTF -- -- CHS3 -- RA1 RB1
Bit 0 RBIF
TMR1IF
Value on: POR, BOR
0000 000x 0000 ---0 xxxx xxxx
Value on all other RESETS
0000 000u 0000 ---0 0000 ---0 uuuu uuuu 0000 0000 --00 ---uuuu 0000 uuuu 0000 1111 1111
INTCON PIE1 PIR1 ADRES ADCON0 ADCON1 PORTA PORTB ANSEL
TMR1IE 0000 ---0
ADC Result Register ADCS1 ADCS0 -- RA7 RB7 -- RA6 RB6 CHS2 VCFG1 RA5 RB5 CHS1 VCFG0 RA4 RB4 ADON -- RA0 RB0
0000 0000 --00 ---xxxx 0000 xxxx 0000 1111 1111
Analog Channel Select
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for ADC conversion.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 77
PIC16C781/782
NOTES:
DS41171A-page 78
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
10.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE
10.1 Control Registers
The DAC module is controlled via two special function registers: DACON0 and DAC. The DACON0 register, shown in Register 10-1: * Enables DAC * Enables output on RB1/AN5/VDAC * Selects reference voltage The DAC register, shown in Register 10-2, sets the output of the DAC.
The Digital-to-Analog Converter (DAC) module generates an output voltage proportional to the value in the 8-bit DAC register (see Figure 10-1). The output of the DAC module can be configured to drive: * The reference input to the ADC module * The reference input to Comparators C1 and C2 * An analog output on pin RB1/AN5/VDAC The voltage reference input selected from: * Analog supply AVDD * Comparator C1 VREF1 * Voltage reference VR to the DAC can be
REGISTER 10-1:
DIGITAL-TO-ANALOG CONVERTER CONTROL REGISTER0 (DACON0: 11Fh)
R/W-0 DAON bit 7 R/W-0 DAOE U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DARS1 R/W-0 DARS0 bit 0
bit 7
DAON: Digital-to-Analog Converter Enable bit 1 = DAC enabled 0 = DAC disabled DAOE: Digital-to-Analog Converter Output Enable bit 1 = Output on the VDAC pin 0 = Output is not available for external use Unimplemented: Read as '0' DARS<1:0>: Digital-to-Analog Converter Voltage Reference Select bits, DACREF 00 = Analog supply, AVDD 01 = Comparator reference, VREF1 pin 10 = Voltage reference, VR 11 = Reserved, do not use Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5-2 bit 1-0
REGISTER 10-2:
DIGITAL-TO-ANALOG CONVERTER REGISTER (DAC: 11Eh)
R/W-0 DA7 bit 7 R/W-0 DA6 R/W-0 DA5 R/W-0 DA4 R/W-0 DA3 R/W-0 DA2 R/W-0 DA1 R/W-0 DA0 bit 0
bit 7-0
DA<7:0>: Digital-to-Analog Converter Digital Input bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set '0' = Bit is cleared
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 79
PIC16C781/782
10.2 Control Register
Note 1: To enable the DAC output as a reference for the ADC module, VCFG<1:0> in ADCON1 must be set. 2: To enable the DAC output as a reference for the Comparator module, C1R/C2R bits (CM1CON0<2>/CM2CON0<2>) must be set. The DAC module is enabled by setting the DAON bit (DACON0<7>). Bits DARS<1:0> (DACON0<1:0>) determine the voltage reference for the DAC module. To output the DAC voltage, the DAOE bit (DACON0<6>) and DAON must be set. To use the DAC output internally, the appropriate reference select bits in the destination module must be set.
FIGURE 10-1:
DAC CONVERTER BLOCK DIAGRAM
DAON DARS<1:0> AVDD VREF1 VR N/C 0 1 DAC Register 2 3 8 DACREF EN DAC Converter
DAOE & DAON VDAC pin
VDAC Voltage for ADC and Comparators Reference
DS41171A-page 80
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
10.3 DAC Configuration
FIGURE 10-2:
Example 10-1 shows a sample configuration for the DAC module. The port pin is configured, AVDD is selected for the voltage reference, and the DAC output is enabled.
Digital Code Input
DAC TRANSFER FUNCTION
EXAMPLE 10-1:
;* ;* ;*
DAC CONFIGURATION
FFh FEh
This code block will configure the DAC for AVDD Voltage Ref, and RB1/AN5/VDAC as output. BANKSEL TRISB BSF TRISB,1 BSF ANSEL,1 BANKSEL CLRF MOVLW MOVWF MOVLW MOVWF DACON0 DAC B'11000000' DACON0 DAC_VALUE DAC ; Select bank 1 ; Set RB1 input ; Set RB1 as analog ; ; ; ; Select Bank 2 DAC to 00 Enable DAC output Set REF = VDD
04h 03h 02h 01h 00h 256 LSb (full scale) 255 LSb 0.5 LSb 1 LSb 2 LSb 3 LSb
4 LSb
; Set DAC output
Analog Output Voltage
10.4
Effects of RESET
A device RESET forces all registers to their RESET state. This forces the following conditions: * * * * DAC module is off Reference input to AVDD Output disabled DAC register is cleared
Offset error measures the first actual transition of a code versus the first ideal transition of a code. Offset error shifts the entire transfer function. Offset error can be calibrated out of a system or introduced into a system through the interaction of the output drive capability with the load impedance. Gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error. This error appears as a change in slope of the transfer function. The difference in gain error to full scale error is that full scale does not take offset error into account. Gain error can be calibrated out by adjusting the reference voltage. Linearity error refers to the uniformity of the voltage change with code change. Linearity errors cannot be calibrated out of the system. Integral non-linearity error measures the actual voltage output versus the ideal voltage output adjusted by the gain error for each code. Differential non-linearity error measures the maximum actual voltage step versus the ideal voltage step. This measure is unadjusted.
10.5
* * * * *
DAC Module Accuracy/Error
The accuracy/error specified for the DAC includes: Integral non-linearity error Differential non-linearity error Gain error Offset error Monotonicity
TABLE 10-1:
Address
REGISTERS/BITS ASSOCIATED WITH DAC
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on All Other RESETS
Name
-- -- -- -- DARS1 DARS0 00-- --00 00-- --00 11Fh DACON0 DAON DAOE 11Eh DAC DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0000 0000 0000 0000 86h TRISB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 1111 1111 1111 1111 9Dh ANSEL AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for DAC conversion.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 81
PIC16C781/782
NOTES:
DS41171A-page 82
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
11.0 OPERATIONAL AMPLIFIER (OPA) MODULE
11.1.1 OPACON REGISTER
The OPA module is enabled by setting the OPAON bit (OPACON<7>). When enabled, the OPA forces the output driver of RB3/AN7/OPA into tri-state to prevent contention between the driver and the OPA output. Clearing the CMPEN bit (OPACON,6>) configures the module as an OPAMP. Setting CMPEN configures the module as a voltage comparator. The GBWP bit (OPACON<0>) controls the speed of the module in both comparator and OPAMP configurations. Setting GBWP results in a Gain Bandwidth Product (GBWP) of 2 MHz typical. Clearing GBWP0 results in a GBWP of the OPA of 70 kHz typical. Note 1: When the OPA module is enabled, the RB3/AN7/OPA pin is driven by the OPAMP output, not by the PORTB driver. Refer to the Electrical specifications for the OPAMP output drive capability. 2: In Comparator mode (CMPEN = 1), an interrupt can be generated using the IOCB feature of RB3. RB3 must be programmed as a digital input with IOCB enabled.
The Operational Amplifier (OPA) Module can be configured as either an OPAMP or Voltage Comparator. The OPA module has the following features: * External connections to all ports * Gain Bandwidth Product selectable: - 70 kHz nom. - 2 MHz nom. * Low leakage inputs * Input Offset Voltage Automatic Calibration Module (ACM) * Input Offset Voltage calibration at a programmable common mode voltage using the DAC * Interrupt-on-change in Comparator mode using IOCB
11.1
Control Registers
The OPACON register, shown in Register 11-1, controls the OPA module. The CALCON register, shown in Register 11-2, controls the Automatic Calibration Module.
FIGURE 11-1:
OPA MODULE BLOCK DIAGRAM
RA0/AN0/OPA+ OPA RA1/AN1/OPARB3/AN7/OPA
OPAON CMPEN GBWP
TO ADC MUX
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REGISTER 11-1: OPAMP CONTROL REGISTER (OPACON: 11Ch)
R/W-0 OPAON bit 7 bit 7 OPAON: OPAMP Enable bit 1 = OPAMP is enabled 0 = OPAMP is disabled CMPEN: Comparator Mode Enable bit 1 = Comparator mode 0 = OPAMP mode Unimplemented: Read as '0' GBWP: Gain Bandwidth Product Select bits 1 = 2 MHz typ. (fast mode) 0 = 70 kHz typ. (slow mode) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 CMPEN U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 GBWP bit 0
bit 6
bit 5-1 bit 0
11.1.2
CALCON REGISTER
Note 1: Auto Calibration must be performed while the module is configured as an OPAMP (CMPEN = 0). Performing Auto Calibration function in the Comparator mode may yield unpredictable results. 2: If the internal 1.2V reference is used for the common mode voltage during Auto Calibration, CALREF = 0 (CALCON<5>), a delay for reference stabilization must be observed before start of calibration. 3: The OPA module shares pins with the ADC module. Performing ADC conversions on the OPA+ or OPA- pins may affect OPAMP stability. 4: When using the DAC as a reference for calibration, CALREF = 1 (CALCON<5>), the VDAC voltage must be within the specified common mode voltage for the OPAMP.
The Automatic Calibration Module (ACM) is an internal state machine which performs an input offset voltage calibration (trim) on the OPA module (see Figure 11-2). Calibration is initiated by setting the CAL bit (CALCON<7>). Upon completion of the calibration sequence, the ACM will clear the CAL bit. If a problem arises in the calibration process, the CALERR flag (CALCON<6>) will be set to indicate the failure to calibrate. Setting CALREF (CALCON<5>) forces calibration at a common mode voltage specified by the output of the DAC module. The DAC module must be enabled prior to calibration. Clearing CALREF will perform the calibration with a common mode voltage of 1.2V. The output pin floats during calibration.
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FIGURE 11-2: AUTO CALIBRATION MODULE BLOCK DIAGRAM
OPAOPA+ 0 1 0 1 OPA
0 1
OPA
CALREF
1.2V nominal
0 Automatic Calibration Module
DAC Module
1
REGISTER 11-2:
CALIBRATION CONTROL REGISTER (CALCON: 110h)
R/S-0 CAL bit 7 R-0 CALERR R/W-0 CALREF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7
CAL: Start and Status bit 1 = Initiates a calibration 0 = Reserved (CAL is cleared by hardware) CALERR: Calibration Error Indicator bit 1 = Error occurred, OPAMP failed 0 = No error CALREF: Calibration Voltage Select bit 1 = VDAC set to desired common voltage reference 0 = 1.2V nominal source (internal voltage source) Note: VDAC must not exceed OPAMP maximum common mode voltage.
bit 6
bit 5
bit 4-0
Reserved: Do not use Legend: S = Cleared by hardware R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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11.2 Configuration as OPAMP or Comparator 11.3 Effects of RESET
A device RESET forces all registers to their RESET state. This disables the OPA module and clears any calibration.
The following example demonstrates calibration of the OPA module as an Operational Amplifier.
EXAMPLE 11-1:
;* ;* ;* ;* ;*
CALIBRATION FOR OPAMP MODE
11.4
OPA Module Performance
This code block will configure the OPA module as an Op Amp, 2 MHz GBWP, and calibrated for a common mode voltage of 1.2V. Routine returns w=0 if calibration good. BANKSEL MOVLW MOVWF BCF BSF OPACON B'10000001' OPACON ; Select Bank 2 ; Op Amp mode & ; 2 MHz GBWP
Common AC and DC performance specifications for the OPA module: * * * * * Common Mode Voltage Range Leakage Current Input Offset Voltage Open Loop Gain Gain Bandwidth Product
CALCON,CALREF; Set 1.2V CALCON,CAL ; Start
CAL_LOOP BTFSC GOTO MOVLW BTFSS CLRW RETURN
CALCON,CAL ; CAL_LOOP ; ERROR_FLAG CALCON,CALERR; ;
Test for end If not, wait Test for error If no, return 0
Common mode voltage range is the specified voltage range for the OPA+ and OPA- inputs, for which the OPA module will perform to within its specifications. The OPA module is designed to operate with input voltages between 0 and VDD-1.4V. Behavior for Common mode voltages greater than VDD-1.4V, or below 0V, are not guaranteed. Leakage current is a measure of the small source or sink currents on the OPA+ and OPA- inputs. To minimize the effect of leakage currents, the effective impedances connected to the OPA+ and OPA- inputs should be kept as small as possible and equal. Input offset voltage is a measure of the voltage difference between the OPA+ and OPA- inputs in a closed loop circuit with the OPA in its linear region. The offset voltage will appear as a DC offset in the output equal to the input offset voltage, multiplied by the gain of the circuit. The input offset voltage is also affected by the Common mode voltage. The OPA has an automatic calibration module which can minimize the input offset voltage of the module. Open loop gain is the ratio of the output voltage to the differential input voltage, (OPA+) - (OPA-). The gain is greatest at DC and falls off with frequency. Gain Bandwidth Product or GBWP is the frequency at which the open loop gain falls off to 0 dB. The lower GBWP is optimized for systems requiring low frequency response and low power consumption.
The following example demonstrates how to configure and calibrate the OPA module as a Voltage Comparator.
EXAMPLE 11-2:
;* ;* ;* ;* ;*
CALIBRATION FOR COMPARATOR MODE
This code block will configure the OPA module as a voltage comparator, slow speed, and calibrated for a common mode voltage of 2.5 V (assumes VDD=5V). Routine returns w=0 if calibration good. BANKSEL MOVLW MOVWF BSF MOVLW MOVWF MOVLW MOVWF OPACON B'10000000' OPACON ; Select Bank 2
; Op Amp mode, ; slow CALCON,CALREF; Common mode=DAC H'0x80' DAC B'10000000' DACON0 CALCON,CAL CALCON,CAL CAL_LOOP
; DAC at VDD/2 ; enable DAC, ; VDD ref ; Start ; Test for end ; If not, wait
BSF CAL_LOOP BTFSC GOTO MOVLW BTFSS CLRW BSF RETURN
ERROR_FLAG CALCON,CALERR; Test for error ; If no, return 0 OPACON,CMPEN ; Comparator mode
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TABLE 11-1:
Address 11Ch 110h 9Dh 86h 85h 11Eh 11Fh
REGISTERS ASSOCIATED WITH THE OPA MODULE
Bit 7 Bit 6 Bit 5 -- AN5 Bit 4 Bit 3 Bit 2 -- -- AN4 -- -- -- -- Bit 1 -- -- AN1 Bit 0 Value on: POR, BOR Value on all other RESETS
Name OPACON CALCON ANSEL TRISB TRISA DAC DACON0
OPAON CMPEN CAL AN7 AN6
GBWP 00-- ---0 00-- ---0 -- AN0 000- ---- 000- ---1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
CALERR CALREF
AN3 AN2
PORTB Data Direction Register PORTA Data Direction Register DA7 DAON DA6 DAOE DA5 -- DA4 -- DA3 DA1 -- -- DA1 DA0
0000 0000 0000 0000
DARS1 DARS0 00-- --00 00-- --00
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for the OPA module.
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NOTES:
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12.0 COMPARATOR MODULE
The comparator module has two separate voltage comparators: Comparator C1 and Comparator C2 (see Figure 12-1). Each comparator offers the following list of features: * * * * * * * * * * Control and configuration register Comparator output available externally Programmable output polarity Interrupt-on-change flags Wake-up from SLEEP Configurable as feedback input to the PSMC Programmable four input multiplexer Programmable reference selections Programmable speed Output synchronization to Timer1 clock input (Comparator C2 only) Setting C1R (CM1CON0<2>) selects the output of the DAC module as the reference voltage for the comparator. Clearing C1R selects the VREF1 input on the RA3/ AN3/VREF1 pin. The output of the comparator is available internally via the C1OUT flag (CM1CON0<6>). To make the output available for an external connection, the C1OE flag (CM1CON0<5>) must be set. If the module is disabled with C1OE set, the output will be driven as shown in Table 12-2: The polarity of the comparator output can be inverted by setting the C1POL flag (CM1CON0<4>). Clearing C1POL results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 12-2.
TABLE 12-1:
OUTPUT STATE VERSUS INPUT CONDITIONS
C1POL 0 0 1 1 C1OUT 0 1 1 0
12.1
Control Registers
Input Condition C1VN > C1VP C1VN < C1VP C1VN > C1VP C1VN < C1VP
Both comparators have separate control and configuration registers: CM1CON0 for C1 and CM2CON0 for C2. In addition, Comparator C2 has a second control register, CM2CON1, for synchronization control and simultaneous reading of both comparator outputs.
12.1.1
COMPARATOR C1 CONTROL REGISTER
The CM1CON0 register (shown in Register 12-1) contains the control and status bits for the following: * * * * * Comparator enable Comparator input selection Comparator reference selection Output mode Comparator speed
Note 1: The internal output of the comparator is latched at the end of each instruction cycle. External outputs are not latched. 2: The C1 interrupt will operate correctly with C1OE set or cleared. 3: For the output of C1 on RB6/C1/ PSMC1A, the PSMC must be disabled and TRISB<6> must be `0'. C1SP (CM1CON0<3>) configures the speed of the comparator. When C1SP is set, the comparator operates at its normal speed. Clearing C1SP operates the comparator in a slower, low power mode.
Setting C1ON (CM1CON0<7>) enables Comparator C1 for operation. Bits C1CH<1:0> (CM1CON0<1:0>) select the comparator input from the four analog pins AN<7:4>. Note: To use AN<7:4> as analog inputs, the appropriate bits must be programmed in the ANSEL register.
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FIGURE 12-1: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
C1CH<1:0> RB0/INT/AN4/VR 0 RB1/AN5/VDAC 1 RB2/AN6 2 RB3/AN7/OPA 3 C1R RA3/AN3/VREF1 0 VDAC 1 C1POL C1VN C1VP C1 2 C1ON C1SP C1OUT To Interrupt and PSMC Logic C1OE RB6/C1/PSMC1A
FIGURE 12-2:
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C2CH<1:0>
RB0/INT/AN4/VR 0 RB1/AN5/VDAC 1 RB2/AN6 2 RB3/AN7/OPA 3
2 C2ON C2SP C2VN C2VP C2
To Interrupt and PSMC Logic C2SYNC C2OUT 0 1 C2POL C2OE RB7/C2/PSMC1B/T1G
C2R RA2/AN2/VREF2 0 VDAC 1 From TMR1 Clock
D
Q Q
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REGISTER 12-1: COMPARATOR C1 CONTROL REGISTER0 (CM1CON0: 119h)
R/W-0 C1ON bit 7 bit 7 C1ON: Comparator C1 Enable bit 1 = C1 Comparator is enabled 0 = C1 Comparator is disabled C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT = 1, C1VP < C1VN C1OUT = 0, C1VP > C1VN If C1POL = 0 (non-inverted polarity): C1OUT = 1, C1VP > C1VN C1OUT = 0, C1VP < C1VN C1OE: Comparator C1 Output Enable bit 1 = C1OUT is present on the RB6/C1/PSMC1A pin(1) 0 = C1OUT is internal only C1POL: Comparator C1 Output Polarity Select bit 1 = C1OUT logic is inverted 0 = C1OUT logic is not inverted C1SP: Comparator C1 Speed Select bit 1 = C1 operates in normal speed mode 0 = C1 operates in low power, slow speed mode C1R: Comparator C1 Reference Select bits (non-inverting input) 1 = C1VP connects to VDAC output 0 = C1VP connects to VREF1 C1CH<1:0>: Comparator C1 Channel Select bits 00 = C1VN of C1 connects to AN4 01 = C1VN of C1 connects to AN5 10 = C1VN of C1 connects to AN6 11 = C1VN of C1 connects to AN7 Note 1: C1OUT will only drive RB6/C1/PSMC1A if: (C2OE = 1) & (C2ON = 1) & (TRISB<7> = 0) & ((SMCON = 0) or ((SMCOM = 0) & (SCEN = 0))). Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R-0 C1OUT R/W-0 C1OE R/W-0 C1POL R/W-0 C1SP R/W-0 C1R R/W-0 C1CH1 R/W-0 C1CH0 bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
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12.1.2 COMPARATOR C2 CONTROL REGISTERS
The output of the comparator is available internally via the C2OUT bit (CM2CON0<6>). To make the output available for an external connection, the C2OE bit (CM2CON0<5>) must be set. Note 1: The internal output of the comparator is latched at the end of each instruction cycle. External outputs are not latched. 2: The C2 interrupt will operate correctly with C2OE set or cleared. An external output is not required for the C2 interrupt. 3: For C2 output on RB7/C2/PSMC1B/T1G: (C2OE=1) & (C2ON=1) & (TRISB<7>=0) & ((SMCON=0) or ((SMCOM=0) & (SCEN=0))). The comparator output, C2OUT, can be inverted by setting the C2POL bit (CM2CON0<4>). Clearing C2POL results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 12-3. C2SP (CM2CON0<3>) configures the speed of the comparator. When C2SP is set, the comparator operates at its normal speed. Clearing C2SP operates the comparator in low power mode.
The CM2CON0 register is a functional copy of the CM1CON0 register described in Section 12.1.1. A second control register, CM2CON1, is also present for control of an additional synchronizing feature, as well as mirrors of both comparator outputs.
12.1.2.1
Control Register CM2CON0
The CM2CON0 register, shown in Register 12-2, contains the control and status bits for Comparator C2. Setting C2ON (CM2CON0<7>) enables Comparator C2 for operation. Bits C2CH<1:0> (CM2CON0<1:0>) select the comparator input from the four analog pins, AN<7:4>. Note 1: To use AN<7:4> as analog inputs, the appropriate bits must be programmed in the ANSEL register. C2R (CM2CON0<2>) selects the reference to be used with the comparator. Setting C2R (CM2CON0<2>) selects the output of the DAC module as the reference for the comparator. Clearing C2R selects the VREF2 input on the RA2/AN2/VREF2 pin.
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REGISTER 12-2: COMPARATOR C2 CONTROL REGISTER0 (CM2CON0: 11Ah)
R/W-0 C2ON bit 7 bit 7 C2ON: Comparator C2 Enable bit 1 = C2 Comparator is enabled 0 = C2 Comparator is disabled C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT = 1, C2VP < C2VN C2OUT = 0, C2VP > C2VN If C2POL = 0 (non-inverted polarity): C2OUT = 1, C2VP > C2VN C2OUT = 0, C2VP < C2VN C2OE: Comparator C2 Output Enable bit 1 = C2OUT is present on RB7/C2/PSMC1B/T1G(1) 0 = C2OUT is internal only C2POL: Comparator C2 Output Polarity Select bit 1 = C2OUT logic is inverted 0 = C2OUT logic is not inverted C2SP: Comparator C2 Speed Select bit 1 = C2 operates in normal speed mode 0 = C2 operates in low power, slow speed mode. C2R: Comparator C2 Reference Select bits (non-inverting input) 1 = C2VP connects to VDAC 0 = C2VP connects to VREF2 C2CH<1:0>: Comparator C2 Channel Select bits 00 = C2VN of C2 connects to AN4 01 = C2VN of C2 connects to AN5 10 = C2VN of C2 connects to AN6 11 = C2VN of C2 connects to AN7 Note 1: C2OUT will only drive RB7/C2/PSMC1B/T1G if: (C2OE = 1) & (C2ON = 1) & (TRISB<7> = 0) & ((SMCON = 0) or ((SMCOM = 0) & (SCEN = 0))). Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R-0 C2OUT R/W-0 C2OE R/W-0 C2POL R/W-0 C2SP R/W-0 C2R R/W-0 C2CH1 R/W-0 C2CH0 bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
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12.1.2.2 Control Register CM2CON1
Comparator C2 has one additional feature: its output can be synchronized to the Timer1 clock input. Setting C2SYNC (CM2CON1<0>) synchronizes the output of Comparator 2 to the falling edge of Timer 1's clock input (see Figure 12-1 and Register 12-3). The CM2CON1 register also contains mirror copies of both comparator outputs, MC1OUT and MC2OUT (CM2CON1<7:6>). The ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers.
REGISTER 12-3:
COMPARATOR C2 CONTROL REGISTER1 (CM2CON1: 11Bh)
R-0 bit 7 R-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 C2SYNC bit 0 MC1OUT MC2OUT
bit 7 bit 6 bit 5-1 bit 0
MC1OUT: Mirror Copy of C1OUT (CM1CON0<6>) MC2OUT: Mirror Copy of C2OUT (CM2CON0<6>) Unimplemented: Read as '0' C2SYNC: C2 Output Synchronous Mode bit 1 = C2 output is synchronous to falling edge of TMR1 clock 0 = C2 output is asynchronous Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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12.2 Comparator Configuration
12.2.1
The following examples show the use of the Comparator module in: * A simple voltage comparator configuration synchronized to the Timer 1 clock input. * A comparator input to the PSMC with a programmable DAC reference. * A low power window comparator configuration with interrupt-on-change.
EXAMPLE: C2 SYNCHRONIZED TO T1CKI
In this example, Comparator C2 is configured as a normal voltage comparator synchronized to the T1CKI input. A block diagram of the comparator with external connections is shown in Figure 12-2.
FIGURE 12-3:
COMPARATOR C2 CONFIGURATION WITH OUTPUT SYNCHRONIZED TO T1CKI
PIC16C78X
C2POL RB2/AN6 INPUT RA2/AN2/VREF2 External Reference
+
C2
D CK
Q Q
CM2CON0<6>
RA6/OSC2/CLKOUT/T1CKI External Oscillator
EXAMPLE 12-1:
;* ;* ;* ;* ;*
C2 CONFIGURATION PROGRAM
12.2.2
EXAMPLE: C1 INPUT TO PSMC W/ DAC AS REFERENCE
This code block will configure C2 for normal speed and output polarity, input on AN6, Reference from VREF2, and output synchronization to TMR1 clock. BANKSEL BSF BSF BSF BSF BSF TRISA TRISA,RA2 TRISA,RA6 TRISB,RB2 ANSEL,AN2 ANSEL,AN6 ; ; ; ; Select RA2 as RA6 as RB2 as Bank 1 input input input
In this example, Comparator C1 is configured as a noninverting normal speed voltage comparator input to the PSMC, with a programmable reference voltage. A block diagram of the comparator with external connections is shown in Figure 12-3.
; AN2 as analog ; AN6 as analog ; Select Bank 2 ; Set C2; no out ; VREF2, AN6
BANKSEL CM2CON0 MOVLW B'10001010' MOVWF CM2CON0 BSF
CM2CON1,C2SYNC ; CLK sync
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FIGURE 12-4: CONFIGURATION OF COMPARATOR C1 WITH DAC
PIC16C78X
C1POL = 0 RB3/AN7/OPA INPUT
+
C1OUT C1
PSMC
VDAC
DAC
EXAMPLE 12-2:
;* ;* ;*
PROGRAMMING C1 FOR PSMC FEEDBACK
12.2.3
EXAMPLE: LOW POWER WINDOW COMPARATOR WITH INTERRUPT
This code block will configure Comparator C1 for normal speed and output polarity, input on AN7, and Reference from the DAC BANKSEL BSF BSF BANKSEL CLRF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF TRISA TRISB,RB3 ANSEL,AN7 ; Select Bank 1 ; RB3 as input ; Set RB3 as analog Select Bank 2 DAC=00h Enable, no out DACREF = VDD Trip Level
To form a low power window comparator, Comparators C1 & C2 are configured as follows: * Common input RB0/INT/AN4/VREF * Separate external reference voltages * Programmed for slow speed operation In addition, the output of comparator C2 must be inverted for common polarity with C1. A block diagram of the window comparator with external connections is shown in Figure 12-4.
DACON0 ; DAC ; B'10000000' ; DACON0 ; DAC_VALUE DAC ;
B'10001111' ; C1; no out, CM1CON0 ; VREF1, AN7
FIGURE 12-5:
WINDOW COMPARATOR WITH INTERRUPT PIC16C78X
INPUT
AN4 C2 + VREF2 CLPOL=1 CM2CON1<6>
VOLTAGE REFERENCE
VREF1 + C1 CM2CON1<7> CLPOL=0
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EXAMPLE 12-3:
;* ;* ;* ;* ;* ;* ;* ;*
WINDOW COMPARATOR
Example of Low Power Window Comparator C1 This code block will configure Comparator C1 and C2 for slow speed, C1 non invert, C2 invert, input on AN4, and external References Interrupt service routine included BANKSEL BSF BSF BSF BSF BSF BSF BANKSEL MOVLW MOVWF MOVLW MOVWF TRISA TRISA,2 TRISA,3 TRISB,0 ANSEL,AN2 ANSEL,AN3 ANSEL,AN4 ; ; ; ; Select Bank 1 RA2 input RA3 input Set RB0
; RA2 analog ; RA3 analog ; RB4 analog Select Bank 2 C1: no output VREF1, AN4 C2: no output invert,VREF1,AN4
CM1CON0 ; B'10000000' ; CM1CON0 ; B'10010000' ; CM2CON0 ;
BANKSEL PIE1 ; Select Bank 1 BCF INTCON,GIE ; Disable Int BSF PIE1,C1IE ; Enabl C1&C2 Ints BSF PIE1,C2IE BSF INTCON,PEIE BSF INTCON,GIE ; Enabl Global Ints ;******************************************** ;* WINDOW COMPARATOR ISR with context save WC_INT_SRV_R MOVWF SWAPF MOVWF BANKSEL MOVLW ANDWF MOVWF
W_SAVE ; Save W & STATUS STATUS,W STATUS_SAV PIR1 ; Select Bank 0 B'00110000' ; Save Int PIR1,W WIN_INT
;*** CLEAR C1 INTERRUPT BTFSS GOTO BANKSEL MOVF BANKSEL BCF WIN_INT,C1IF; C1 Int ? TST_C2_INT CM1CON0 ; Select Bank 2 CM1CON0,F ; Clear C2 mismatch PIR1 ; Select Bank 0 PIR1,C1IF ; Clear C2 Int
;*** CLEAR C2 INTERRUPT TXT_C2_INT BTFSS GOTO BANKSEL MOVF BANKSEL BCF
WIN_INT,C2IF; C2 int? USER_ISR CM2CON0 ; Select Bank 2 CM2CON0,F ; Clear C2 mismatch PIR1 ; Select Bank 0 PIR1,C1IF ; Clear C2 int
USER_ISR ;*** USER INTERRUPT ROUTING ;* SWAPF MOVWF SWAPF SWAPF RETFIE STATUS_SAVE,W; Restore W & ; STATUS STATUS W_SAVE,F W_SAVE,W ; Return
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12.3 Effects of RESET
A RESET forces all registers to their RESET state. This disables both comparators.
TABLE 12-2:
Address 119h 11Ah 11Bh 85h 86h 05h 06h 9Dh 0Ch 8Ch Name
REGISTERS ASSOCIATED WITH THE COMPARATOR MODULE
Bit 7 C1ON C2ON Bit 6 C1OUT C2OUT Bit 5 Bit 4 Bit 3 Bit 2 C1R C2R -- Bit 1 C1CH1 C2CH1 -- Bit 0 C1CH0 C2CH0 C2SYNC Value on: POR, BOR
0000 0000 0000 0000 00-- ---0 1111 1111 1111 1111
Value on all other RESETS
0000 0000 0000 0000 00-- ---0 1111 1111 1111 1111 uuuu 0000 uuuu 0000 1111 1111 0000 ---0 0000 ---0
CM1CON0 CM2CON0 TRISA TRISB PORTA PORTB ANSEL PIR1 PIE1
C1OE C1POL C1SP C2OE C2POL C2SP -- -- --
CM2CON1 MC1OUT MC2OUT
PORTA Data Direction Register PORTB Data Direction Register RA7 RB7 AN7 LVDIF LVDIE RA6 RB6 AN6 ADIF ADIE RA5 RB5 AN5 C2IF C2IE RA4 RB4 AN4 C1IF C1IE RA3 RB3 AN3 -- -- RA2 RB2 AN2 -- -- RA1 RB1 AN1 -- -- RA0 RB0 AN0 TMR1ON TMR1IE
xxxx 0000 xxxx 0000 1111 1111 0000 ---0 0000 ---0
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for comparator.
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13.0 PROGRAMMABLE SWITCH MODE CONTROLLER (PSMC)
All pulse start and duty cycle limit timing features of the PSMC are derived from the internal CPU clock. Block diagrams for the PSMC are shown in Figure 13-1 through Figure 13-3.
The Programmable Switch Mode Controller module provides all the necessary features to implement a pulsed feedback control system. The PSMC generates a pulse output based on its analog feedback. Feedback from the comparator is programmable, allowing: * Single or dual channel feedback * Programmable reference voltage selection * Programmable polarity The pulse output of the PSMC is also programmable, featuring either Pulse Width (PWM) or Pulse Skip (PSM) Modulation. In PSM, a fixed duty cycle is generated or skipped, based on feedback. In PWM a feedback controlled pulse width is generated. In addition, the output configuration of the PSMC is programmable, enabling the following features: * A single output * A single output plus a slope compensation output * Dual alternating outputs
13.1
Pulse Width Modulation (PWM)
In the PWM mode, the PSMC (shown in Figure 13-1 and Figure 13-2) is a timer-driven set/RESET pulse generator. Pulses are initiated by the internal counter chain. Following the completion of the programmable minimum duty cycle, the output pulse is terminated by either a high to low transition on the comparator output, or by the programmable maximum duty cycle (see Table 13-1 and Table 13-2). The resulting output is a variable duty cycle pulse with: * * * * Programmable frequency Feedback specified duty cycle Programmable minimum duty cycle including 0% Programmable maximum duty cycle
FIGURE 13-1:
PSMC MODULE IN SINGLE OUTPUT PWM MODE (SIMPLIFIED BLOCK DIAGRAM)
EXAMPLE Min DC Period New Cycle
FOSC
1:1
1:2
1:4 1:8
Max D/C SC Switch
SMCCL1 SMCCL0
3 S1 S0
2
1
0
C1OUT RB6/C1/ PSMC1A RB7/C2/ PSMC1B/T1G ASSUMES 4-bit Counter 4 New Cycle DC = Duty Cycle
HIGH IMPEDANCE S1APOL=0 SMCCS=0 S1APOL Q Set Dominant R S
HIGH IMPEDANCE
PSMC CLK
SCEN=1 PWM/PSM=1 SMCON=1 SMCOM=0
RB6/C1/PSMC1A
MAXDC<1:0>
2 PSMC Max Controller DC
MINDC<1:0>
2
SC Switch
VDD RB7/C2/PSMC1B/T1G N
C1POL C1OUT C1 C2POL C2 SMCCS C2OUT SCEN
Comparator Module
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FIGURE 13-2: PSMC MODULE IN DUAL ALTERNATING OUTPUT PWM MODE (SIMPLIFIED BLOCK DIAGRAM)
EXAMPLE Min DC Period New Cycle A FOSC 1:1 1:2 1:4 1:8 New Cycle B Max DC SMCCL1 SMCCL0 3 S1 S0 PSMC CLK 2 1 0 C1OUT RB6/C1/ PSMC1A RB7/C2/ PSMC1B/T1G ASSUMES 4-bit Counter 4 New Cycle A PSMC Controller New Cycle B Max DC S1BPOL C1OUT C1 C2POL C2 Comparator Module SMCCS C2OUT Q Set Dominant R S RB7/C2/PSMC1B/T1G DC = Duty Cycle S1APOL=0 S1BPOL=0 S1APOL S Q SMCCS=0 PWM/PSM=1 SMCON=1 SMCOM=1 Min DC Period Min DC
RB6/C1/PSMC1A
MAXDC<1:0>
2
Set Dominant R
MINDC<1:0>
2
C1POL
TABLE 13-1:
Time
PSMC1A OUTPUT SEQUENCE IN PWM MODE USING C1 COMPARATOR ONLY
MINDC<1:0> 00 non-zero non-zero x x q = Prior State 0 = Inactive C1OUT H L x x HL LH x 1 = Active H = High PSMC1A Output Signal 01 0 01 1 q 0 0 q 0 L = Low
Beginning of PWM cycle
During Min Duty Cycle After Min Duty Cycle, Before Max Duty Cycle Max Duty Cycle Legend: x = Don't Care
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TABLE 13-2:
Time Beginning of PWM cycle
PSMC1A OUTPUT SEQUENCE IN PWM MODE USING C1 AND C2 COMPARATORS
MINDC<1:0> 00 C1OUT H L x x x HL LH H x x 1 = Active C2OUT H x L x x H x HL LH x H = High L = Low PSMC1A Output Signal 01 0 0 01 1 q0 0 q0 0 q0
During Min Duty Cycle After Min Duty Cycle, Before Max Duty Cycle
non-zero non-zero x
Max Duty Cycle Legend: x = Don't Care q = Prior State
x 0 = Inactive
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13.1.1 PULSE SKIP MODULATION (PSM)
In PSM (Pulse Skip Modulation), the PSMC operates as a fixed duty cycle pulse generator, with its output gated by the analog feedback (see Figure 13-3). Immediately prior to the initiation of a pulse, the analog feedback is sampled. If the comparator output = H, a pulse is initiated and held active for the programmed duty cycle. If the comparator output = L, no pulse is initiated and the PSMC waits for the start of the next pulse (see Table 13-3 and Table 13-4). In this mode, both the frequency and duty cycle of the output pulse are programmable. The analog feedback gates the presence or absence of the pulse on a pulse-by-pulse basis.
FIGURE 13-3:
PSMC MODULE IN SINGLE OUTPUT PSM MODE (SIMPLIFIED BLOCK DIAGRAM)
EXAMPLE Period New Cycle
FOSC
:1
:2
:4
:8
Programmed DC Select DC SC Switch 15/16 Period
SMCCL1 SMCCL0
3 S1 S0
2
1
0
C1OUT RB6/C1/ PSMC1A RB7/C2/ PSMC1B/T1G ASSUMES 4-bit Counter 4 DC = Duty Cycle
HIGH IMPEDANCE S1APOL=0 SMCCS=0 S1APOL Q Set Dominant R S
HIGH IMPEDANCE
PSMC CLK
SCEN=1 PWM/PSM=0 SMCON=1 SMCOM=0
RB6/C1/PSMC1A
New Cycle
DC<1:0> 2
PSMC Max Controller DC SC Switch
VDD RB7/C2/PSMC1B/T1G N
C1POL C1OUT C1 C2POL C2 SMCCS C2OUT SCEN
Comparator Module
TABLE 13-3:
PSMC1A OPERATION IN PSM MODE USING C1 COMPARATOR ONLY
Time C1OUT H L x x 0 = Inactive 1 = Active H = High L = Low PSMC1A Output Signal 01 0 No Change 1 10
Beginning of PSM cycle During Pulse End of Pulse Legend: x = Don't Care
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TABLE 13-4: PSMC1A OUTPUT SEQUENCE IN PSM MODE USING C1 AND C2 COMPARATORS
Time Beginning of PSM cycle C1OUT H L x x x x 0 = Inactive 1 = Active C2OUT H x L x x x H = High L = Low PSMC1A Output Signal 01 0 0 No Change No Change 10
During Pulse Duty Cycle After Pulse Duty Cycle Legend: x = Don't Care
13.1.2
SINGLE OR DUAL OUTPUT
13.1.3
SLOPE COMPENSATION
The PSMC has the capability to operate with either a single output, or dual alternating outputs. In the single output mode, the PSMC generates an output pulse on PSMC1A output only. The pulses are at the programmed frequency, and are variable between the programmed minimum and maximum duty cycle limits. In the dual output mode, the PSMC generates output pulses which alternate between PSMC1A and PSMC1B. The pulses generated at each output are generated at one half of the programmed frequency, and between 50% of the programmed minimum. and 50% maximum of the output duty cycle. The maximum duty cycle for either output is 50%.
An optional feature of the PSMC single output mode is the ability to configure the PSMC1B output for use as a slope compensation ramp generator. In this mode, the PSMC1B output is pulled low for the last 1/16 of each pulse cycle. Connecting the PSMC1B output to an RC network, similar to Figure 13-4, results in a positive going pseudo ramp function. This pseudo ramp function is useful as an offset function for the loop error signal in unstable conditions at a duty cycle of greater than 50%.
Note:
When the Slope Compensation switch is enabled (SMCOM = 0, and SCEN = 1), the S1BPOL bit has no effect (see RC Network on next page for more detail).
FIGURE 13-4:
t=0
SLOPE COMPENSATION (SC) SWITCH OPERATION
t = 15/16T VDD PIC16C78X VDD DC = duty cycle T = Period 150 - On C SC Switch - Off VSS VSS To Slope Compensation Circuit R PSMC1B PSMC Module
PSMC1A
PWM Signal on PSMC1A pin
SC Switch on PSMC1B pin
Voltage across C
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13.2 Control Registers
The PSMC is controlled by means of two special function registers: PSMCCON0 and PSMCCON1. The PSMCCON0 register (Register 13-1) contains control bits for: * Frequency of the output pulse * Minimum and maximum duty cycle in PWM mode * Fixed duty cycle in PSM mode The PSMCCON1 register (Register 13-2) contains the control bits for: * Enabling the PSMC module * Setting the PSMC mode * Configuring inputs and outputs In the PWM mode, the MAXDC <1:0> bits (PSMCCON0 <3:2>) specify the maximum duty cycle limit. In the PSM mode, the DC<1:0> bits (PSMCCON0<1:0>) specify the fixed duty cycle.
13.2.2
PSMCCON1 REGISTER
To enable the PSMC operation, the SMCON bit in the PSMCCON1 register must be set (see Register 13-2). The PWM/PSM bit (PSMCCON1<1>) configures the output mode of the PSMC. When the PWM/PSM bit is set, the PSMC is configured for a PWM output. When the PWM/PSM bit is cleared, a fixed duty cycle pulse is output. The SMCCS bit (PSMCCON1<0>) sets the input mode. When the SMCCS bit is set, the PSMC is configured for two inputs: C1 and C2. When cleared, only Comparator C1 is used. SMCOM bit (PSMCCON1<1>) determines the number of outputs from the PSMC. When SMCOM is set, both PSMC1A and PSMC1B are active. When SMCOM is cleared, only the PSMC1A output is active and the PSMC1B output is available for another function. S1APOL and S1BPOL control the polarity of the PSMC outputs. Setting the polarity bit configures the corresponding output for an active low state. Clearing the bit results in an active high output. The SCEN bit (PSMCCON1<2>) enables the slope compensation output. When SCEN is set (and SMCOM is cleared) the PSMC1B output is configured to generate a slope compensation signal.
Note:
Following RESET, both the PSMC1A and PSMC1B outputs are held tri-state until the PSMC is configured. Driver circuitry for all power MOSFET transistors must have a resistor bias to turn off the transistor in the event of tri-state conditions, on either PSMC1A or PSMC1B, to prevent excessive stress on the MOSFET's and their associated circuitry.
13.2.1
PSMCCON0 REGISTER
The SMCCL<1:0> bits in the PSMCCON0 register, are used to set the pulse frequency of the PSMC. Note: Changing SMCCL<1:0> bits with the PSMC enabled (SMCON=1) can result in unpredictable output. Always disable PSMC before changing SMCCL<1:0>.
In the PWM mode, the MINDC <1:0> bits (PSMCCON0 <5:4>) specify the minimum duty cycle.
Note:
PSMC outputs must have their corresponding direction bits cleared in TRISB; TRISB<6>: for PSMC1A, and TRISB<7> for PSMC1B.
TABLE 13-5:
PSMC OUTPUT MODES
PSMC FUNCTION SMCOM SCEN 0 1 x TRISB<6> 0 0 0 TRISB<7> * 0 0 PORTB
Single Output Single Output + Slope Compensation
0 0
Dual Output 1 Legend: x = Don't Care *As needed for other functions (such as C2, RB7, T1G).
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REGISTER 13-1: PSMC CONTROL REGISTER0 (PSMCCON0: 111h)
R/W-0 bit 7 bit 7-6 SMCCL<1:0>: Clock Frequency Select bits 00 = Output frequency for single output mode is FOSC/128 01 = Output frequency for single output mode is FOSC/64 10 = Output frequency for single output mode is FOSC/32 11 = Output frequency for single output mode is FOSC/16 MINDC<1:0>: Minimum Duty Cycle Select bits for PWM Mode 00 = Min duty cycle of 0 01 = Min duty cycle of 1/8 10 = Min duty cycle of 1/4 11 = Min duty cycle of 3/8 MAXDC<1:0>: Maximum Duty Cycle Select bits for PWM Mode 00 = Max duty cycle of 1/2 01 = Max duty cycle of 5/8 10 = Max duty cycle of 3/4 11 = Max duty cycle of 15/16 DC<1:0>: Duty Cycle Select bits for PSM Mode 00 = Duty cycle of 1/8 01 = Duty cycle of 3/8 10 = Duty cycle of 5/8 11 = Duty cycle of 15/16 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 MINDC1 R/W-0 MINDC0 R/W-0 MAXDC1 R/W-0 MAXDC0 R/W-0 DC1 R/W-0 DC0 bit 0 SMCCL1 SMCCL0
bit 5-4
bit 3-2
bit 1-0
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REGISTER 13-2: PSMC CONTROL REGISTER1 (PSMCCON1: 112h)
R/W-0 SMCON bit 7 bit 7 SMCON: PSMC Module Enable bit 1 = PSMC module on 0 = PSMC module off S1APOL: PSMC1A Output Polarity Control bit 1 = PSMC1A output signal is asserted low 0 = PSMC1A output signal is asserted high S1BPOL: PSMC1B Output Polarity Control bit 1 = PSMC1B output signal is asserted low 0 = PSMC1B output signal is asserted high Unimplemented: Read as '0 SCEN: Slope Compensation Output Enable bit If SMCOM = 1: x = This bit is ignored If SMCOM = 0: 1 = Slope Compensation Switch on PSMC1B pin is enabled 0 = Slope Compensation Switch on PSMC1B pin is not enabled. PSMC1B pin is available for other functions. SMCOM: PSMC Output Mode bit 1 = Dual alternating output mode. The module outputs are available on the PSMC1A and PSMC1B pins. 0 = Single output mode. The module output is available on the PSMC1A pin. PWM/PSM: PSMC Modulation Mode Select bit 1 = PWM mode (Pulse Width Modulation) 0 = PSM mode (Pulse Skipping Modulation) SMCCS: PSMC Comparator Select bit 1 = PSMC module uses inputs from both C1OUT and C2OUT 0 = SMC module uses input from C1OUT only Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 S1APOL R/W-0 S1BPOL U-0 -- R/W-0 SCEN R/W-0 SMCOM R/W-0 PWM/PSM R/W-0 SMCCS bit 0
bit 6
bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
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13.3 Configuration
The programmable nature of the PSMC lends itself to a wide variety of applications involving current or voltage management. The following examples are intended to provide suggested applications for the PSMC. The examples are not complete designs, but rather block diagrams of some potential applications of the PSMC. For a broader list of applications, including supporting math and firmware examples, please refer to Microchip web page for applicable Application Notes. The inner current loop is a pulsed current source driven by the PSMC. During the active phase of the output pulse, the inner loop builds up a current flow in inductor L1. The current in L1 is monitored by the current transformer. The output of the transformer is offset by the ramp from the slope compensation network R3/C1 and then fed into the comparator. When the voltage (proportional to the current flow in L1, offset by the slope compensation) exceeds the error voltage from the OPAMP, Q1 is turned off and L1 discharges through D1 into CMAIN for the remainder of the period. The outer voltage loop monitors the output voltage across CMAIN using R1/R2. The reference voltage from the DAC is subtracted, generating the raw error voltage. The raw error voltage is filtered by the OPAMP and routed to Comparator C1 in the inner current loop. The phase compensation output of the PSMC acts to improve loop stability by adding a pseudo-ramp waveform to the current sense transformer feedback in the inner loop. In conditions where the charge phase of the cycle is greater then 50%, the increased current feedback reduces the current charge in L1, slowing the charging of CMAIN. The result is a reduction in the overall loop gain for duty cycles of >50%, maintaining loop stability.
13.3.1
EXAMPLE BOOST LC SWITCHING POWER SUPPLY
In this example, the PSMC controls the boost configuration switching power supply in Figure 13-5. The PSMC is configured as a two feedback loop PWM, current mode, switching power supply controller. The inner current feedback loops consist of: * * * * * * * * * * PSMC MOSFET driver Power MOSFET Q1 Inductor L1 Current transformer Comparator C1 Diode D1 CMAIN OPAMP feedback filter DAC reference
The outer voltage feedback loop consists of:
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FIGURE 13-5: EXAMPLE BOOST CONFIGURATION LC SWITCHING POWER SUPPLY
+DCRAW
PIC16C781/782
L1 MOSFET DRIVER RB6/C1/PSMC1A A PSMC RB7/C2/PSMC1B R3 VDD SC C1 RB3/AN7/OPA Q1 CMAIN R1 R2 RA1/AN1/OPACURRENT TRANSFORMER D1
+
LOAD
OPA RA4/AN0/OPA+
RA3/AN3/VREF1
C1 RB2/AN6
RB1/AN5/VDAC VREF DAC
Note:
The OPAMP, Comparator and DAC must be configured, prior to enabling the PSMC to prevent unpredictable operation which may stress the power MOSFET transistors.
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EXAMPLE 13-1: PSMC CONFIGURATION EXAMPLE
;* This code block will configure the PSMC and ;* all additional peripherals for a boost mode ;* switching power supply. ;* ;* Order of configuration ;* 1. PORTA/B I/O and analog configured ;* 2. DAC enabled, configured, and preset ;* 3. Op Amp enabled and configured ;* 4. Comparator C1 enabled and configured ;* 5. PSMC configured ;* 6. PSMC enabled
********************************************************** ;* This code block will configure all analog ports. BANKSEL MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF TRISA B'00001011' TRISA B'11001110' TRISB B'11101011' ANSEL ; Select Bank 1 ; Set RA0,1,& 3 as inputs ; Set RB1,2,3,6 & 7 as inputs ; Configure RA0, RA1, RA3, ; RB1, RB2, RB3 as analog
;********************************************************************** ;* This code block will configure the DAC for VDD as ;* DACREF, and RB1/AN5/VDAC as an output BANKSEL CLRF MOVLW MOVWF DACON0 DAC B'11000000' DACON0 ; Select Bank 2 ; Set DAC to safe value ; Enable DAC, output ; and set DACREF = VDD
MOVLW OUTPUT_VALUE MOVWF DAC ; Set DAC output level ;********************************************************************** ;* This code block will configure the OPA module as an ;* Op Amp, with a 2MHz GBWP MOVLW MOVWF B'10000001' OPACON ; Set Op Amp mode and ; 2MHz GBWP
;************************************************************************* ;* This code block will configure Comparator C1 ;* for normal speed and output polarity, ;* input on AN6, and Reference from the VREF1 MOVLW MOVWF B'10001010 CM1CON0 ; Set C1, no ext out, norm ; speed & pol, VREF1, AN6
;************************************************************************ ;* This code block will configure the PSMC module ;* for PWM, FOSC/128, Single in, Single pulse out, slope comp out ;* Non-inverting out, DC min = 0%, DC max = 75% MOVLW MOVWF MOVLW MOVWF BSF B'00001000' PSMCCON0 B'00001010' PSMCCON1 PSMCCON1,SMCON
; ; ; ;
Set DCmin 0, DCmax 75, FOSC/128 Set PWM Sngl in, Sngl out non-invert Slope comp Enable PSMC
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13.3.2 EXAMPLE BUCK LC SWITCHING POWER SUPPLY
The outer voltage loop monitors the output voltage across CMAIN via R1/R2. The reference voltage from the DAC is subtracted from the feedback voltage to generate the raw error voltage. The raw error voltage is then filtered by the OPAMP and routed to Comparator C1 in the inner current loop. In using two alternating outputs, the outputs are limited to less than 50% duty cycle. As a result, the circuit avoids the problems associated with instability at duty cycles of >50%. For more information concerning the design of switching power supplies, refer to: Switching Power Supply Design, by Abraham I. Pressman, published by McGraw Hill (ISBN 0-07-052236-7).
In this example, the PSMC controls the buck configuration switching power supply in Figure 13-6. The PSMC is configured as a typical PWM, current mode, switching power supply controller. The inner current feedback loops consist of: * * * * * * * * * * PSMC 2 MOSFET drivers Power MOSFETs Q1 and Q2 Inductors L1 and L2 Current transformer Comparator C1/C2 Diodes D1, D2, D3, and D4 CMAIN OPAMP feedback filter DAC reference
The outer voltage feedback loop consists of: Note: Following RESET, both the PSMC1A and PSMC1B outputs are held tri-state until the PSMC is configured. Driver circuitry for all power MOSFET transistors must have a resistor bias to turn off the transistor in the event of tri-state conditions on either output to prevent undo stress on the MOSFET's and their associated circuitry.
The circuit uses two feedback loops, an inner current control loop, and an outer voltage loop. The inner loop is further divided into two channels, Q1/L1, and Q2/L2. The PSMC operates a PWM output, alternately driving Q1 for a cycle, then driving Q2 the next. During the active phase of either output pulse, the inner loop builds up a current flow in the output's inductor, proportional to the error voltage received from the OPAMP. The current flow in the inductor begins the charging of CMAIN. When the voltage (proportional to the current flow in the inductor) exceeds the error voltage: * * * * The comparator resets the PSMC output The MOSFET is turned off The flyback diode forward biases The inductor discharges into CMAIN for the remainder of the period.
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EXAMPLE 13-2: EXAMPLE PSMC CONFIGURATION FOR A BUCK MODE SWITCHING POWER SUPPLY
;* PSMC Initialization ;* This code block will configure the PSMC ;* and all additional peripherals for a buck ;* mode switching power supply. ;* ;* Order of configuration ;* 1. PORTA/B I/O and analog configured ;* 2. DAC enabled, configured, and preset ;* 3. Op Amp enabled and configured ;* 4. Comparator C1 enabled and configured ;* 5. PSMC configured ;* 6. PSMC enabled ;******************************************** ;* This code block will configure all analog ports. ; BANKSEL TRISA ; Select Bank 1 MOVLW B'00001011' MOVWF TRISA ; Set RA0,1,& 3 as inputs MOVLW B'11001110 MOVWF TRISB ; Set RB1,2,3,6 & 7 as inputs MOVLW B'11101011' MOVWF ANSEL ; Set AN0,1,3,5,6 & 7 as analog ;******************************************************* ;* This code block will configure the DAC for VDD as ;* DACREF, and RB1/AN5/VDAC as an output. BANKSEL CLRF MOVLW MOVWF MOVLW MOVWF DACON0 DAC B'11000000' DACON0 OUTPUT_VALUE DAC ; Select Bank 2 ; Set DAC to safe value ; Enable DAC, output ; and set DACREF = VDD
; Set dAC output level
;******************************************************* ;* This code block will configure the OPA module ;* as an Op Amp, with a 3 MHZ GBWP MOVLW MOVWF B'10000001' OPACON ; Set Op Amp mode and ; 2 MHz GBWP
;******************************************************** ;* This code block will configure Comparator C1 ;* for normal speed and output polarity, ;* input on AN6, and Reference from the VREF1 MOVLW MOVWF B'10001010' CM1CON0 ; Set C1; no ext out, norm ; speed & pol, VREF1, AN6
;******************************************************** ;* This code block will configure the PSMC module ;* for PWM, Fosc/128, Single input, Single output ;* Non-inverting out, DC min = 0%, DC max = 50% MOVLW MOVWF MOVLW MOVWF BSF B'0000000' PSMCCON0 B'00000110' PSMCCON1 PSMCCON1,SMCON
; Set DCmin 0, DCmax 50, Fosc/128 ; Set PWM, 1 in, 2 out, noninvert ; Enable PSMC
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FIGURE 13-6: EXAMPLE BUCK CONFIGURATION LC POWER SUPPLY
+VIN CURRENT TRANSFORMER MOSFET DRIVER
PIC16C781/782
Q1
RB6/C1/PSMC1A A PSMC RB7/C2/PSMC1B/T1G B
L1
D3
D1 CMAIN MOSFET DRIVER Q2 L2 RA3/AN3/VREF1 D4 LOAD
+ C1 RB2/AN6 RB3/AN7/OPA RA1/AN1/OPAOPA + RA0/AN0/OPA+
D2
R1
R2
RB1/AN5/VDAC VREF DAC
13.3.3
EXAMPLE MOTOR SPEED CONTROL
The algorithm (used to determine the values output by the DAC module) depends on: * mechanical system connected to the motor * motor characteristics * characteristics of the high current drive An analysis of the mechanics of the system and the design of an appropriate control algorithm is beyond the scope of this Data Sheet. Therefore, the designer should consult a text dealing with the design of motor speed controls and feedback control system, in general, for the necessary design guidance.
In Figure 13-7, the PSMC acts as a speed control for a brushless DC motor. The direction of the current in the motor winding is set by feedback from a Hall effect position sensor on the motor. The sensor switches the phase in the motor in response to the rotation of the rotor so that the magnetic field rotates just ahead of the rotor, pulling it in the desired direction. The speed at which the rotor spins is a function of the mechanical load on the rotor and the current in the field winding. Speed control is accomplished by monitoring the speed via the Hall effect sensor and regulating the current in the winding appropriately. The winding current is regulated by the PSMC to be proportional to the value supplied by the DAC module. The feedback loop is closed by software making periodic measurement of the rotor speed using the Hall Effect sensor/Timer1 and adjusting the output value of the DAC appropriately.
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EXAMPLE 13-3: PERIPHERAL CONFIGURATION EXAMPLE
************************************************ ;* This code block will configure the PSMC and ;* all additional peripherals for a motor speed ;* control. ;* ;* Order of configuration ;* 1. PORTA/B I/O and analog configured ;* 2. DAC enabled, configured, and preset ;* 3. Op Amp enabled and configured ;* 4. Comparator C1 enabled and configured ;* 5. PSMC configured ;* 6. PSMC enabled ;* ************************************************ ;* This code block will configure all analog ports. BANKSEL MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF TRISA B'01000011' TRISA B'00001100' TRISB B'11000011' ANSEL ; Select Bank 1 ; Set RA0,1 & 6 as inputs ; Set RB2 & 3 as inputs ; Set AN0,1,6,& 7 as analog
;************************************************ ;* This code block will configure the DAC for VR as ;* DACREF, and no output. BANKSEL BSF BANKSEL CLRF MOVLW MOVWF MOVLW MOVWF REFCON REFCON, VREN DACON0 DAC B'10000010' DACON0 OUTPUT_VALUE DAC
; Enable VR ; Select Bank 2 ; Set DAC to safe value ; Enable DAC, no output ; and set DACREF = VR
; Set DAC output level
;************************************************ ;* This code block will configure the OPA module ;* as an Op Amp, with a 2 MHz GBWP MOVLW MOVWF B'10000001' OPACON ; Set Op Amp mode and ; 2 MHz GBWP
;************************************************ * This code block will configure Comparator C1 * for normal speed and output polarity, * input on AN6, and Reference from the VDAC MOVLW MOVWF B'10001110' CM1CON0 ; Set C1; no ext out, norm ; speed & pol, VDAC, AN6
;************************************************ ;* This code block will configure the PSMC module ;* for PWM, Fosc/16, Single input, Single output ;* Non-inverting out, DC min = 0%, DC max = 94% MOVLW MOVWF MOVLW MOVWF BSF B'11001100' PSMCCON0 B'00000010' PSMCCON1 PSMCCON1,SMCON
; Set DCmin 0, DCmax 94, Fosc/16 ; Set PWM, Sngl in/out, noninvert ; Enable PSMC
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FIGURE 13-7: EXAMPLE BRUSHLESS D.C. MOTOR CONTROL
VMOTOR
PIC16C781/782
H-BRIDGE DRIVER FOSC RB6/C1/PSMC1A /16 S Q ENABLE PHASE R RSENSE RB2/AN6 C1
BRUSHLESS D.C. MOTOR HALL EFFECT SENSOR
RB3/AN7/OPA
RA0/AN0/OPA+ OPA VREF FIRMWARE FEEDBACK CONTROL RA1/AN1/OPA-
DAC
RA6/OSC2/CLKOUT/T1CKI TIMER 1
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2001 Microchip Technology Inc.
PIC16C781/782
13.4 Effects of SLEEP and RESET
A device RESET forces all registers to their RESET state. This disables the PSMC and resets its outputs to digital inputs. It is good design practice to include a failsafe resistor bias in all power transistor drive circuitry. The fail-safe circuit should disable the power device when the PSMC output drive transistor is held tri-state. This protects the power device and its associated circuitry from the stress of prolonged operation without feedback. Placing the PIC16C781/782 into SLEEP mode will stop the main oscillator for the microcontroller. The PSMC derives its timing from the main oscillator. Therefore, operation of the PSMC will halt when the microcontroller enters SLEEP mode. To prevent damage, the outputs of the PSMC are gated so that they are driven to their inactive state whenever the device enters SLEEP mode. When the microcontroller wakes up, the PSMC resumes operation per its previously programmed configuration.
TABLE 13-6:
Address Name
REGISTERS ASSOCIATED WITH THE PSMC
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS
86h,186h TRISB 11Ah 119h 111h 112h CM2CON0 CM1CON0
PORTB Data Direction Register C2ON C1ON C2OUT C1OUT C2OE C1OE C2POL C1POL -- C2SP C1SP SCEN C2R C1R C2CH1 C1CH1 DC1
1111 1111 1111 1111
C2CH0 0000 0000 0000 0000 C1CH0 0000 0000 0000 0000 DC0
0000 0000 0000 0000
PSMCCON0 SMCCL1 SMCCL0 MINDC1 MINDC0 MAXDC1 MAXDC0 PSMCCON1 SMCON S1APOL S1BPOL
SMCOM PWM/PSM
SMCCS 000- 0000 000- 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for PSMC.
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Preliminary
DS41171A-page 115
PIC16C781/782
NOTES:
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Preliminary
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PIC16C781/782
14.0 SPECIAL FEATURES OF THE CPU
14.1 Configuration Bits
The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped in program memory location 2007h.
These devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features include: * Oscillator selection * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Programmable Brown-out Reset (PBOR) * Interrupts * Watchdog Timer (WDT) * Programmable Low Voltage Detection (PLVD) * SLEEP * Code protection * ID locations * In-Circuit Serial ProgrammingTM (ICSPTM) Several oscillator options are available to allow the part to fit the application. The INTRC oscillator options save system cost while the LP crystal option saves power. A set of configuration bits is used to select various options. The CPU also features a Watchdog Timer (WDT), which can be enabled either through a configuration bit during programming, or by the software. For added reliability, the WDT runs off its own internal RC oscillator instead of the main CPU clock. In addition to the WDT, the CPU incorporates both an Oscillator Start-up Timer and a Power-up Timer. The Oscillator Start-up Timer (OST) is intended to hold the chip in RESET until the crystal oscillator has stabilized. The Power-up Timer (PWRT) holds the CPU in a fixed RESET delay of 72ms (nominal) on Power-up Resets (POR and PBOR), while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can awaken from SLEEP through: * External RESET * Watchdog Timer Wake-up * Interrupt Additional information on special features is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
Note:
Address 2007h is beyond the user program memory space, which can be accessed only during programming.
Some of the core features provided may not be necessary for each application in which a device may be used. The configuration word bits allow these features to be configured/enabled/disabled as necessary. These features include: * * * * * Code Protection PBOR Trip Point Power-up Timer Watchdog Timer Device Oscillator Mode
As can be seen in Table 14-1, some additional configuration word bits have been provided for Brown-out Reset trip point selection.
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Preliminary
DS41171A-page 117
PIC16C781/782
REGISTER 14-1:
CP bit13 bit 13-12, 9-8 bit 11-10 CP: Program Memory Code Protection bits 1 = Code Protection off 0 = All program memory is protected(1) BORV<1:0>: Brown-out Reset Voltage bits 00 = PBOR set to 4.5V 01 = PBOR set to 4.2V 10 = PBOR set to 2.7V 11 = PBOR set to 2.5V Unimplemented: Read as `1' BODEN: Brown-out Detect Reset Enable bit(1) 1 = Brown-out Detect Reset enabled 0 = Brown-out Detect Reset disabled MCLRE: RA5/MCLR Pin Function Select bit 1 = RA5/MCLR pin function is MCLR 0 = RA5/MCLR pin function is digital input, MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC<2:0>: Oscillator Selection bits FOSC<2:0> 000 001 010 011 100 101 110 111 OSCILLATOR RA6/OSC2/CLKOUT/T1CKI LP XT HS EC INTRC INTRC RC RC Crystal/Resonator Crystal/Resonator Crystal/Resonator Digital I/O Digital I/O CLKOUT Digital I/O CLKOUT RA7/OSC1/CLKIN Crystal/Resonator Crystal/Resonator Crystal/Resonator CLKIN Digital I/O Digital I/O RC RC CP
CONFIGURATION WORD FOR PIC16C781/782 DEVICE (CONFIG:2007h)
CP CP -- BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 bit0
BORV1 BORV0
bit 7 bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1: All of the CP bits must be given the same value to enable code protection.
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2001 Microchip Technology Inc.
PIC16C781/782
14.2
14.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 14-1:
CERAMIC RESONATORS
Ranges Tested:
The PIC16C781/782 can be operated in eight different oscillator modes. The user can program three configuration bits FOSC<2:0> to select one of these eight modes: Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator External Resistor and Capacitor (with and without CLKOUT) * INTRC Internal 4 MHz/37 kHz (with and without CLKOUT) * EC External Clock * * * * LP XT HS RC
Mode XT
Freq
C1
C2
455 kHz 68 - 100 pF 68 - 100 pF 2.0 MHz 15 - 68 pF 15 - 68 pF 4.0 MHz 15 - 68 pF 15 - 68 pF HS 8.0 MHz 10 - 68 pF 10 - 68 pF 16.0 MHz 10 - 22 pF 10 - 22 pF These values are for design guidance only. See Notes 1 and 2 in shaded box. In this test, all resonators used did not have built-in capacitors.
TABLE 14-2:
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF
14.2.2
LP, XT AND HS MODES
Osc Type LP XT
In LP, XT, or HS modes, a crystal or ceramic resonator is connected to the RA7/OSC1/CLKIN and RA6/OSC2/ CLKOUT/T1CKI pins to establish oscillation (Figure 14-1). The PIC16C781/782 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may yield a frequency outside of the crystal manufacturers' specifications.
Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz
FIGURE 14-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
PIC16C781/782
HS
4 MHz 8 MHz 20 MHz
C1(1)
RA7/OSC1/ CLKIN XTAL RA6/OSC2 CLKOUT/ T1CKI Rs(2) RF(3)
These values are for design guidance only. See Notes 1 and 2 in shaded box.
To Internal Logic SLEEP
C2(1)
Note 1: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 2: Higher capacitance increases the stability of oscillator but also increases the start-up time.
Note 1: See Table 14-1 and Table 14-2 for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen.
14.2.3
EC MODE
In applications where the clock source is external, the PIC16C781/782 should be programmed to select the EC (External Clock) mode. In this mode, the RA6/ OSC2/CLKOUT/T1CKI pin is available as an I/O pin. See Figure 14-2 for illustration. To minimize power supply current drawn, the EC oscillator input should be driven by a CMOS level square wave.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 119
PIC16C781/782
FIGURE 14-2: EC OSC CONFIGURATION
RA7 Clock from ext. system I/O PIC16C781/782 RA7/OSC1/CLKIN
FIGURE 14-3:
VDD
RC OSCILLATOR MODE
PIC16C781/782 REXT RA7/OSC1/ CLKIN Internal Clock
RA6/OSC2/CLKOUT/ T1CKI
CEXT
14.2.4
RC MODE
VSS FOSC/4 RA6/OSC2/CLKOUT/I1CKI
For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of: * supply voltage * resistor (REXT) and capacitor (CEXT) values * operating temperature In addition, the oscillator frequency varies from unit to unit due to normal process variation. The difference in lead frame capacitance between package types also affects the oscillation frequency, especially for low CEXT values. The user should allow for variations due to tolerance of external R and C components used. Figure 14-3 shows how the RC combination is connected to the PIC16C781/782. For REXT values below 2.2 k, the oscillator operation may become unstable or stop completely. For very high REXT values (e.g., 1 M or greater), the oscillator becomes sensitive to: * noise * humidity * leakage Microchip recommends keeping REXT between 3 k and 100 k. Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as board trace capacitance or package lead frame capacitance. See Section 18.0 for RC frequency variation from part to part due to normal process variation. The variation is greater for large values of R (since leakage current variations affect RC frequency more for large R) and for small values of C (since variations of input capacitance affect RC frequency more). See Section 18.0 for variation of oscillator frequency due to VDD for given REXT and CEXT values (or for frequency variation due to operating temperature for given R, C, and VDD values).
14.2.5
INTRC MODE
The internal RC oscillator provides a fixed 4 MHz/37 kHz (nominal) system clock at VDD = 5V and 25C. See Section 18.0 for information on variations over voltage and temperature ranges. The INTRC oscillator does not run during RESET.
14.2.6
DUAL SPEED OPERATION FOR INTRC MODE
A software programmable slow speed mode is available with the INTRC oscillator. This feature allows the firmware to dynamically toggle the oscillator speed between normal and slow frequencies. The nominal slow frequency is 37 kHz. Applications that require low current power savings, but cannot tolerate putting the part into SLEEP, may use this mode. The OSCF bit (PCON<3>) is used to control dual speed mode. See the PCON Register, Register 2-6, for details. When changing the INTRC internal oscillator speed, there is a brief period of time when the processor is inactive. When the speed changes from fast to slow, the processor inactive period is in the range of 100 S to 300 S. For a speed change from slow to fast, the processor is inactive between 1.25 S and 3.25 S, nominal.
14.2.7
CLKOUT
In the INTRC and RC modes, the PIC16C781/782 can be configured to provide a clock out signal by programming the configuration word. The oscillator frequency, divided by 4, can be used for test purposes or to synchronize other logic. In the INTRC and RC modes, if the CLKOUT output is enabled, CLKOUT is held low during RESET.
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PIC16C781/782
14.3 RESET
The PIC16C781/782 devices have several different RESETS. These RESETS are grouped into two classifications: power-up and non power-up. The power-up type RESETS are the Power-on and Brown-out Resets, which assume the device VDD was below its normal operating range for the device's configuration. The non power-up type RESETS assume normal operating limits were maintained before/during and after the RESET. * Power-on Reset (POR) * Programmable Brown-out Reset (PBOR) * Non Power-up (MCLR) Reset during normal operation * MCLR Reset during SLEEP * WDT Reset (during normal operation) Some registers are not affected in any RESET condition. Their status is unknown on a Power-up Reset and unchanged in any other RESET. Most other registers are placed into an initialized state upon RESET. However, they are not affected by a WDT Reset during SLEEP, because this is considered a WDT Wake-up, which is viewed as the resumption of normal operation. Several status bits have been provided to indicate which RESET occurred (see Table 14-4). See Table 14-5 for a full description of RESET states of special registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 14-4. These devices have a MCLR noise filter in the MCLR Reset path. The filter detects and ignores small pulses. It should be noted that a WDT Reset does not drive MCLR pin low.
FIGURE 14-4:
RA5/MCLR/VPP
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External RESET
SLEEP WDT Time-out Module VDD VDD Rise Detect
Power-on Reset
Programmable BODEN Brown-out RA7/OSC1/ CLKIN OST/PWRT OST 10-bit Ripple Counter
S
R
Q
Chip_Reset
PWRT Dedicated Oscillator 10-bit Ripple Counter
Enable PWRT
Enable OST
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 121
PIC16C781/782
14.4 Power-on Reset (POR) 14.5 Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when a VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, simply enable the internal MCLR feature. This eliminates external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Section 17.0 for details. For a slow rise time, see Figure 14-5. Two delay timers (PWRT on OST) are provided, which hold the device in RESET after a POR (dependent upon device configuration), so that all operational parameters have been met prior to releasing the device to resume/begin normal operation. When the device starts normal operation (exits the RESET condition), device operating parameters (i.e., voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions, or if necessary an external POR circuit may be implemented to delay end of RESET for as long as needed. The Power-up Timer provides a fixed TPWRT time-out on power-up type RESETS only. For a POR, the PWRT is invoked when the POR pulse is generated. For a BOR, the PWRT is invoked when the device exits the RESET condition (VDD rises above BOR trip point). The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT's time delay is designed to allow VDD to rise to an acceptable level. A configuration bit (PWRT) is provided to enable/disable the PWRT for the POR only. For a BOR the PWRT is always available regardless of the configuration bit setting. The power-up time delay varies from chip-to-chip due to VDD, temperature and process variation. See DC parameters for details.
14.6
Programmable Brown-out Reset (PBOR)
FIGURE 14-5:
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD RAMP)
The Programmable Brown-out Reset module is used to generate a RESET when the supply voltage falls below a specified trip voltage. The trip voltage is configurable to any one of four voltages provided by the BORV<1:0> configuration word bits. Configuration bit BODEN can disable (if clear/programmed), or enable (if set), the Brown-out Reset circuitry. If VDD falls below the specified trip point for longer than TBOR (see Parameter 35, Section 17.0, Table 17-6), the brown-out situation resets the chip. A RESET may not occur if VDD falls below the trip point for less than TBOR. The chip remains in Brown-out Reset until VDD rises above VBOR. The Power-up Timer is invoked at that point and keeps the chip in RESET an additional TPWRT. If VDD drops below VBOR while the Power-up Timer is running, the chip goes back into a Brown-out Reset and the Power-up Timer is reinitialized. Once VDD rises above VBOR, the Power-up Timer again begins a TPWRT time delay.
VDD D
VDD PIC16C781/782 R R1 MCLR C
Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
14.7
Time-out Sequence
On power-up, the time-out sequence is as follows: First, PWRT time-out is invoked by the POR pulse. When the PWRT delay expires, the Oscillator Start-up Timer is activated. The total time-out varies depending on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there is no time-out at all. Figure 14-6, and Figure 14-9 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs expire. Then, bringing MCLR high begins execution immediately. This is useful for testing purposes or to synchronize more than one PICmicro microcontroller operating in parallel. Table 14-5 shows the RESET conditions for some special function registers.
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PIC16C781/782
14.8 Power Control/Status Register (PCON)
Clearing the OSCF (PCON<3>) enables oscillation at 37kHz, setting OSCF returns the oscillator to operation at 4MHz. The Watchdog Timer is a free running, on-chip dedicated oscillator and timer, which does not require any external components to operate. The WDT provides a system RESET in the event that software does not execute a CLRWDT instruction within a specified interval. For reliability, the WDT will run even if the CPU clock has been stopped (for example, by the execution of a SLEEP instruction). During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to awaken and resume normal operation (Watchdog Timer Wake-up). The WDT can be enabled either by setting the WDTE bit in the configuration register during programming, or by setting the WDTON bit (PCON<4>).
The Power Control/Status Register, PCON, has two status bits that provide indication of which power-up type RESET occurred. PCON<0> is Brown-out Reset Status bit, BOR. Bit BOR is set on a Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if bit BOR cleared, indicating a BOR occurred. However, if the brown-out circuitry is disabled, the BOR bit is a "Don't Care" bit and is considered unknown upon a POR. PCON<1> is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. When the CPU is running under the INTRC oscillator mode, the frequency of the INTRC oscillator can be switched to a power saving 37 kHz (nominal) mode.
TABLE 14-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up Brown-out PWRTE = 0 PWRTE = 1 1024TOSC -- TPWRT + 1024TOSC TPWRT TPWRT + 1024TOSC TPWRT Wake-up from SLEEP 1024TOSC --
Oscillator Configuration XT, HS, LP EC, RC, INTRC
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 123
PIC16C781/782
REGISTER 14-2: POWER CONTROL REGISTER (PCON: 8Eh)
U-0 -- bit 7 bit 7-5 bit 4 Unimplemented: Read as '0' WDTON: WDT Software Enable bit If WDTE bit (Configuration Word <3>) = 1: This bit is not writable, always reads `1' If WDTE bit (Configuration Word <3>) = 0: 1 = WDT is enabled 0 = WDT is disabled and cleared OSCF: Oscillator Speed bit (pending on new internal oscillator decision) INTRC mode: 1 = 4 MHz typical 0 = 37 kHz typical All other oscillator modes: Ignored Unimplemented: Read as '0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR x = Bit is unknown W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared U-0 -- U-0 -- R/W-q WDTON R/W-1 OSCF U-0 -- R/W-q POR R/W-x BOR bit 0
bit 3
bit 2 bit 1
bit 0
'q' = Value depends on condition
TABLE 14-4:
POR 0 0 0 1 1 1 1 1 BOR 1 x x 0 1 1 1 1
STATUS BITS AND THEIR SIGNIFICANCE
TO 1 0 x 1 0 0 u 1 PD 1 x 0 1 1 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP Bit Significance
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Preliminary
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PIC16C781/782
TABLE 14-5: RESET CONDITION FOR SPECIAL REGISTERS
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP, GIE = 0 Interrupt wake-up from SLEEP, GIE = 1 Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1 0004h STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu uuu1 0uuu PCON Register ---0 1-01 ---0 1-uu ---0 1-uu ---0 1-uu ---0 u-uu ---0 1-u0 ---u u-uu ---u u-uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'.
FIGURE 14-6:
VDD MCLR INTERNAL POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 14-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 125
PIC16C781/782
TABLE 14-6: INITIALIZATION CONDITION FOR ALL REGISTERS
Power-On Reset or Brown-Out Reset xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 MCLR Reset or WDT Reset uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu PC + 1(1) Register W (not a mapped register) INDF TMR0 PCL
STATUS 0001 1xxx 000q quuu(2) uuuq quuu(2) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA xxxx 0000 uuuu 0000 uuuu uuuu PORTB xxxx xx00 uuuu uu00 uuuu uu00 PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 000x 0000 000u uuuu uuqq PIR1 0000 ---0 0000 ---0 0000 ---u CALCON 000- ---000- ---uuu- ---TMR1L xxxx xxxx uuuu uuuu uuuu uuuu TMR1H xxxx xxxx uuuu uuuu uuuu uuuu T1CON -000 0000 -uuu uuuu -uuu uuuu PSMCCON0 0000 0000 0000 0000 uuuu uuuu PSMCCON1 000- 0000 000- 0000 uuu- uuuu CM1CON0 0000 0000 0000 0000 uuuu uuuu CM2CON0 0000 0000 0000 0000 uuuu uuuu CM2CON1 00-- ---0 00-- ---0 uu-- ---u OPACON 00-- ---0 00-- ---0 uu-- ---u ADRES xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 0000 0000 0000 0000 uuuu uuuu OPTION_REG 1111 1111 1111 1111 uuuu uuuu TRISA 1111 1111 1111 1111 uuuu uuuu TRISB 1111 1111 1111 1111 uuuu uuuu PIE1 0000 ---0 0000 ---0 uuuu ---u PCON ---0 1-qq ---0 1-uu ---u u-uu DAC 0000 0000 0000 0000 uuuu uuuu DACON0 00-- --00 00-- --00 uu-- --uu WPUB 1111 1111 1111 1111 uuuu uuuu IOCB 1111 0000 1111 0000 uuuu uuuu REFCON ---- 00----- 00----- uu-LVDCON --00 0101 --00 0101 --uu uuuu ANSEL 1111 1111 1111 1111 uuuu uuuu ADCON1 --00 -----00 -----uu ---PMDATL xxxx xxxx uuuu uuuu uuuu uuuu PMADRL xxxx xxxx uuuu uuuu uuuu uuuu PMDATH --xx xxxx --uu uuuu --uu uuuu PMADRH ---- xxxx ---- uuuu ---- uuuu PMCON1 1--- ---0 1--- ---0 1--- ---0 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 2: See Table 14-5 for RESET value for specific condition.
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PIC16C781/782
FIGURE 14-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 14-9:
SLOW VDD RISE TIME (MCLR TIED TO VDD)
5V VDD MCLR 0V
INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET
(1)
Note 1: This time depends on the oscillator circuit used.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 127
PIC16C781/782
14.9 Interrupts
The devices have up to eight sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. When an interrupt is serviced, the GIE bit is cleared to disable any further interrupt. The return address is pushed onto the stack and the PC is loaded with 0004h. Once in the Interrupt Service Routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency is three or four instruction cycles. The exact latency depends on when the interrupt event occurs. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set, regardless of the status of the GIE bit. The GIE bit is cleared on RESET. The "return from interrupt" instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts. The RB0/INT/AN4/VR pin interrupt, the RB port Interrupt-on-Change (IOCB) and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the special function register PIR1. The corresponding interrupt enable bits are contained in special function register PIE1, and the peripheral interrupt enable bit is contained in special function register INTCON.
14.9.1
INT INTERRUPT
External interrupt on RB0/INT/AN4/VR pin is edge triggered: either rising, if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The INT interrupt can awaken the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following a wake-up sequence. See Section 14.12 for details on SLEEP mode.
FIGURE 14-10:
INTERRUPT LOGIC
T0IF T0IE LVDIF LVDIE C2IF C2IE C1IF C1IE ADIF ADIE TMR1IF TMR1IE INTF INTE RBIF RBIE PEIF PEIE GIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
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Preliminary
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14.9.2 TMR0 INTERRUPT EXAMPLE 14-1:
An overflow (FFh 00h) in the TMR0 register sets the flag bit, T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit, T0IE (INTCON<5>) (Section 2.5).
SAVING STATUS, W, AND PCLATH REGISTERS
14.9.3
PORTB INTERRUPT-ON-CHANGE (IOCB)
An input change on PORTB<7:0> sets flag bit RBIF (INTCON<0>). The PORTB pin(s) which can individually generate interrupt are selectable in the IOCB register. The interrupt can be enabled/disabled by setting/ clearing enable bit RBIE (INTCON<4>) (Section 2.5). PORTB must be configured as a digital input.
14.10 Context Saving During Interrupts
During an interrupt, only the PC is saved on the stack. At minimum, W and STATUS should be saved to preserve the context for the interrupted program. All registers that may be corrupted by the Interrupt Service Routine (ISR), such as PCLATH or FSR, should be saved. Example 14-1 stores and restores the STATUS, W and PCLATH registers. The register, W_TEMP, is defined in Common RAM, the last 16 bytes of each bank that may be accessed from any bank. The STATUS_TEMP and PCLATH_TEMP are defined in bank 0. The example: a) b) c) d) e) f) g) Stores the W register. Stores the STATUS register in bank 0. Stores the PCLATH register in bank 0. Executes the ISR code. Restores the PCLATH register. Restores the STATUS register. Restores W.
#define W_TEMP 0x70 #define STATUS_TEMP 0x71 #define PCLATH_TEMP 0x72 org 0x04 ; Int Vector MOVWF W_TEMP ; Save W MOVF STATUS,w MOVWF STATUS_TEMP ; save STATUS MOVF PCLATH,w MOVWF PCLATH_TEMP ; save PCLATH : (Interrupt Service Routine) : MOVF PCLATH_TEMP,w MOVWF PCLATH MOVF STATUS_TEMP,w MOVWF STATUS SWAPF W_TEMP,f ; swapf loads W SWAPF W_TEMP,w ; w/o affect STATUS RETFIE
14.11 Watchdog Timer (WDT)
The Watchdog Timer uses a free running, on-chip RC oscillator, which does not require any external components. This oscillator is independent from the processor clock. The WDT runs even if the main clock of the device has been stopped (for example, by execution of a SLEEP instruction). During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register is cleared upon a Watchdog Timer time-out. The WDT can be permanently enabled by programming the configuration bit WDTE, or by software via the WDTON bit in the Power Control register (PCON: 8EH). See Section 14.8 and Section 14.1. WDT time-out period values may be found in the Electrical Specifications. Values for the WDT prescaler may be assigned using the OPTION_REG register. Note 1: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT. 2: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count is cleared, but the prescaler assignment is not changed.
Note:
The W_TEMP, STATUS_TEMP and PCLATH_TEMP are defined in the common RAM area (70h - 7Fh) to avoid register bank switching during context save and restore.
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FIGURE 14-11: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 5-2) WDTE(2) WDT Timer 0 M 1U X Postscaler 8 8 - to - 1 MUX PS<2:0>(1)
WDTON(3)
PSA(1)
To TMR0 (Figure 5-2) 0 MUX 1 PSA(1)
WDT Time-out Note 1: PSA and PS<2:0> are bits in the OPTION_REG register. 2: WDTE bit in the configuration word. 3: WDTON bit in the PCON register.
TABLE 14-7:
Address 2007h 81h,181h 8Eh
SUMMARY OF WATCHDOG TIMER REGISTERS
Name Bit 7 -- RBPU -- Bit 6 BODEN INTEDG -- Bit 5 MCLRE T0CS -- Bit 4 PWRTE T0SE WDTON Bit 3 WDTE PSA OCSF Bit 2 FOSC2 PS2 -- Bit 1 FOSC1 PS1 BOR Bit 0 FOSC0 PS0 POR
Config. Bits(1) OPTION_REG PCON
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 14-1 for the full description of the Configuration Word bits.
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14.12 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer is cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode: * place all I/O pins at either VDD, or VSS, * ensure no external circuitry is drawing current from the I/O pin, * power-down all peripherals, * disable external clocks. Pull all I/O pins that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from onchip pull-ups on PORTB should be considered. Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.
14.12.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction completes as a NOP. Therefore, the WDT and WDT postscaler are not cleared, the TO bit is not set, and PD bits are not cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device immediately awakens from SLEEP. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler are cleared, the TO bit is set, and the PD bit is cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
14.12.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, PORTB IOCB, or any Peripheral Interrupts.
External MCLR Reset causes a device RESET. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. 4. 5. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. ADC conversion (when ADC clock source is RC). Programmable low voltage detect. Comparator C1 or C2 interrupt-on-change. OPA in Comparator mode using IOCB.
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FIGURE 14-12:
OSC1 CLKOUT(3) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency(2) TOST(1)
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
TOST = 1024TOSC (drawing not to scale). This delay applies to LP, XT and HS modes only. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
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15.0 INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXXX instruction set summary in Table 15-2 lists byte-oriented, bitoriented, and literal and control operations. Table 151 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 15-2 lists the instructions recognized by the MPASMTM assembler. Figure 15-1 shows the general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16CXXX products, do not use the OPTION and TRIS instructions.
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
TABLE 15-1:
Field f W b k x
OPCODE FIELD DESCRIPTIONS
Description
FIGURE 15-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 k (literal)
d
PC TO PD
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 Program Counter Time-out bit Power-down bit
0
0
The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations
k = 8-bit immediate value
CALL and GOTO instructions only
13
11 OPCODE
10 k (literal)
0
k = 11-bit immediate value
A description of each instruction is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
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TABLE 15-2:
Mnemonic, Operands
PIC16CXXX INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS Status Notes Affected LSb
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS
ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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15.1
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add Literal and W [label] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register. Operation: Status Affected: Description: k ANDWF Syntax: Operands: AND W with f [label] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. f,d
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [label] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. f,d
BCF Syntax: Operands: Operation: Status Affected: Description:
Bit Clear f [label] BCF 0 f 127 0b7 0 (f) None Bit 'b' in register 'f' is cleared. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND Literal with W [label] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register. k
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [label] BSF 0 f 127 0b7 1 (f) None Bit 'b' in register 'f' is set. f,b
BTFSS Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Set [label] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit 'b' in register 'f' is '0', the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.
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BTFSC Syntax: Operands: Operation: Status Affected: Description: Bit Test, Skip if Clear [label] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit 'b' in register 'f' is '1', the next instruction is executed. If bit 'b', in register 'f', is '0', the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. f,d
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [label] CLRF 0 f 127 00h (f) 1Z Z The contents of register 'f' are cleared and the Z bit is set. f
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [label] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register 'f' are decremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 1, the next instruction is executed. If the result is 0, then a NOP is executed instead, making it a 2TCY instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead, making it a 2TCY instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a twocycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal 'k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
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MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (destination) Z The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected. Status Affected: Description: RETLW Syntax: Operands: Operation: Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move Literal to W [ label ] k (W) None The eight-bit literal 'k' is loaded into W register. The don't cares will assemble as 0's. MOVLW k 0 k 255
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
MOVWF Syntax: Operands: Operation: Status Affected: Description:
Move W to f [ label ] (W) (f) None Move data from W register to register 'f'. MOVWF f 0 f 127
RLF Syntax: Operands: Operation: Status Affected: Description:
Rotate Left f through Carry [ label ] RLF f,d 0 f 127 d [0,1] See description below C The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'.
C Register f
NOP Syntax: Operands: Operation: Status Affected: Description:
No Operation [ label ] None No operation None No operation. NOP
RETFIE Syntax: Operands: Operation: Status Affected:
Return from Interrupt [ label ] None TOS PC, 1 GIE None RETFIE
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RRF Syntax: Operands: Operation: Status Affected: Description: Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
C Register f
SUBWF Syntax: Operands: Operation: Description:
Subtract W from f [ label ] 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. SUBWF f,d
Status Affected: C, DC, Z
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. SLEEP
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W register. If 'd' is 1, the result is placed in register 'f'.
Status Affected: Description:
SUBLW Syntax: Operands: Operation: Description:
Subtract W from Literal [ label ] 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal 'k'. The result is placed in the W register. SUBLW k
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR Literal with W [label] 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal 'k'. The result is placed in the W register.
Status Affected: C, DC, Z
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XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [label] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
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16.0 DEVELOPMENT SUPPORT
The MPLAB IDE allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files - absolute listing file - machine code The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the costeffective simulator to a full-featured emulator with minimal retraining. The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPICTM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Entry-Level Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ(R) Demonstration Board
16.2
MPASM Assembler
The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCU's. The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects. * User-defined macros to streamline assembly code. * Conditional assembly for multi-purpose source files. * Directives that allow complete control over the assembly process.
16.1
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows(R)-based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor * A project manager * Customizable toolbar and key mapping * A status bar * On-line help
16.3
MPLAB C17 and MPLAB C18 C Compilers
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI `C' compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 141
PIC16C781/782
16.4 MPLINK Object Linker/ MPLIB Object Librarian 16.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: * Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. * Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: * Easier linking because single libraries can be included instead of many smaller files. * Helps keep code maintainable by grouping related modules together. * Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted.
The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows environment were chosen to best make these features available to you, the end user.
16.7
ICEPIC In-Circuit Emulator
16.5
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multiproject software development tool.
The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present.
DS41171A-page 142
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
16.8 MPLAB ICD In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in realtime.
16.11 PICDEM 1 Low Cost PICmicro Demonstration Board
The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB.
16.9
PRO MATE II Universal Device Programmer
The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode.
16.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board
The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad.
16.10 PICSTART Plus Entry Level Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 143
PIC16C781/782
16.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board
The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
16.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware.
16.15 KEELOQ Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchip's HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters.
DS41171A-page 144
Preliminary
2001 Microchip Technology Inc.
24CXX/ 25CXX/ 93CXX
PIC14000
HCSXXX
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
PIC16F62X
PIC16C7XX
PIC16F8XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
PIC18FXXX
MCRFXXX
MCP2510
TABLE 16-1:
MPLAB(R) Integrated Development Environment
a
a
a
a
a
a
a
a
a
a
a
a
a
aa
aa
MPLAB(R) C17 C Compiler
Software Tools
MPLAB(R) C18 C Compiler
MPASMTM Assembler/ MPLINKTM Object Linker
a
a
Programmers Debugger Emulators
Demo Boards and Eval Kits
2001 Microchip Technology Inc.
aaa
aaa
aa
**
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
MPLAB(R) ICE In-Circuit Emulator
ICEPICTM In-Circuit Emulator
a
* *
a
a
a
a
a
a
a
MPLAB(R) ICD In-Circuit Debugger
a
**
a
a
a
PICSTART(R) Plus Entry Level Development Programmer
a
**
a
a
a
a
a
a
a
a
a
a
a
a
a
a
PRO MATE(R) II Universal Device Programmer
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
DEVELOPMENT TOOLS FROM MICROCHIP
Preliminary
a a a a a

PICDEMTM 1 Demonstration Board
PICDEMTM 2 Demonstration Board
a
a
a
a
PICDEMTM 3 Demonstration Board
a
PICDEMTM 14A Demonstration Board
a
PICDEMTM 17 Demonstration Board
a
KEELOQ(R) Evaluation Kit
aa
KEELOQ(R) Transponder Kit
microIDTM Programmer's Kit
aa
125 kHz microIDTM Developer's Kit
125 kHz Anticollision microIDTM Developer's Kit
a
13.56 MHz Anticollision microIDTM Developer's Kit
a
PIC16C781/782
DS41171A-page 145
MCP2510 CAN Developer's Kit
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB(R) ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices.
a
PIC16C781/782
NOTES:
DS41171A-page 146
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
17.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Ambient temperature under bias....................................................................................................... -55C to +125C Storage temperature ......................................................................................................................... -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) ................................... -0.3V to (VDD + 0.3 V) Voltage on VDD with respect to VSS .......................................................................................................-0.3 to +7.5 V Maximum voltage between AVDD and VDD pins............................................................................................... 0.3 V Maximum voltage between AVSS and VSS pins ............................................................................................... 0.3 V Voltage on MCLR with respect to VSS................................................................................................ -0.3 V to +8.5 V Voltage on RA4 with respect to Vss ...................................................................................................0.3 V to +10.5 V Total power dissipation(1) (PDIP, SOIC)............................................................................................................. 1.0 W Total power dissipation(1) (SSOP) .................................................................................................................... 0.65 W Maximum current out of VSS pin ..................................................................................................................... 300 mA Maximum current into VDD pin ........................................................................................................................ 250 mA Input clamp current, IIK (VI < 0 or VI > VDD .................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD ............................................................................................. 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by PORTA and PORTB (combined)........................................................................... 200 mA Maximum current sourced by PORTA and PORTB (combined....................................................................... 200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 147
PIC16C781/782
FIGURE 17-1:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 0 4 10 Frequency (MHz) 20 25
PIC16C781/782 VOLTAGE-FREQUENCY GRAPH, -40C TA +85C
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 17-2:
5.5 4.54.0 VDD (Volts)
PIC16LC781/782 VOLTAGE-FREQUENCY GRAPH, -40C TA +85C
2.7
0
4
10 Frequency (MHz)
20
25
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS41171A-page 148
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
17.1 DC Characteristics: Power Supply
DC CHARACTERISTICS: PIC16C781/782, PIC16LC781/782 (INDUSTRIAL)
Standard Operating Conditions (unless otherwise stated) Operating temperature-40C TA +85C for industrial Characteristic Supply Voltage Supply Voltage (PIC16LC781/782) RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Supply Current(2) Min 4.0 4.5 2.7 4.5 -- -- 0.05 -- -- -- -- D020 D020A IPD IOPA Power-down Current(3) Operational Amplifier -- -- -- Typ -- -- -- -- 1.5 TBD -- TBD TBD TBD TBD TBD 1.5 TBD TBD IVC* Voltage Comparators C1 and C2 -- -- IADC* D021 D026 IWDT* IAD* IPLVD* IPBOR* 1A FOSC Digital to Analog Converter (DAC) Watchdog Timer Analog-to-Digital Converter (ADC) Programmable Low Voltage Detect Programmable Brown-out Reset LP Oscillator, Operating Freq. INTRC Oscillator Operating Freq. XT Oscillator Operating Freq. HS Oscillator Operating Freq. * Note 1: 2: 9 -- -- 0 0 -- -- -- TBD TBD TBD TBD TBD TBD TBD -- 4 37 -- -- Max 5.5 5.5 5.5 5.5 -- -- -- TBD TBD TBD TBD TBD 19 TBD TBD TBD TBD TBD TBD TBD TBD TBD 200 -- -- 4 20 Units V -- V V V V V/ms mA mA mA mA A A mA mA mA mA mA mA mA mA mA kHz MHz kHz MHz MHz See section on Power-on Reset for details See section on Power-on Reset for details. PWRT enabled FOSC = 20 MHz, VDD = 5.5V* HS Oscillator FOSC = 20 MHz, VDD = 4.5V HS Oscillator FOSC = 4 MHz, VDD = 4.0V* XT, RC w/CLKOUT FOSC = 32 kHz, VDD = 4.0V LP Oscillator VDD = 5.5V VDD = 4.0V VDD = 5.0V, GBWP = 0 VDD = 5.0V, GBWP = 1 VDD = 5.0V, VID>100 mV C1SP = 0 VDD = 5.0 , VID>100 mV C1SP = 1 VDD = 5.0V VDD = 4.0V VDD = 5.5V, ADC not converting VDD = 4.0V VDD = 5.0V All temperatures All temperatures, OSCF = 1 All temperatures, OSCF = 0 All temperatures All temperatures Conditions XT, EC, RC, INTRC Oscillator HS Oscillator XT, EC, RC, INTRC Oscillator HS Oscillator
TABLE 17-1:
DC CHARACTERISTICS Param No. D001 D001A D002* D003 D004* D010 Sym VDD VDD VDR VPOR SVDD IDD
3:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins configured as inputs, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins configured as iputs and tied to VDD or VSS.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 149
PIC16C781/782
17.2 DC Characteristics: Input/Output Pins
DC CHARACTERISTICS: PIC16C781/782, PIC16LC781/782 (INDUSTRIAL)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and Operating voltage VDD range as described in DC spec Section 17-1 Characteristic Input Low Voltage I/O ports: with TTL buffer with Schmitt Trigger buffer MCLR OSC1 (in XT, HS, LP and EC) Input High Voltage I/O ports: with TTL buffer Min Typ Max Units Conditions
TABLE 17-2:
DC CHARACTERISTICS Param No. Sym
VIL D030 D030A D031 D032 D033 VIH D040 D040A D041 D042 D042A D070 IPURB
VSS VSS VSS VSS VSS
-- -- -- -- -- -- -- -- -- -- -- 250
0.15VDD 0.8V 0.2VDD 0.2VDD 0.3 VD
V V V V V
For entire VDD range 4.5V VDD 5.5V For entire VDD range
with Schmitt Trigger buffer MCLR OSC1 (XT, HS, LP and EC) PORTB Weak Pull-up Current Per Pin Input Leakage Current(1,2) I/O ports (with digital functions) I/O ports (with analog functions) RA5/MCLR/VPP OSC1 Output Low Voltage I/O ports (Includes CLKOUT) Output High Voltage
2.0 (0.25VDD + 0.8V) 0.8VDD 0.8VDD 0.7VDD 50
VDD VDD VDD VDD VDD 400
V V V V
4.5V VDD 5.5V For entire VDD range For entire VDD range
V A VDD = 5V, VPIN = VSS
D060
IIL
-- -- -- --
-- -- -- --
1 100 5 5
D060A IIL D061 D063
A Vss VPIN VDD, Pin at hi-impedance nA Vss VPIN VDD, Pin at hi-impedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS, LP and EC osc configuration V V V IOL = 8.5 mA, VDD = 4.5V IOH = -3.0 mA, VDD = 4.5V RA4 pin
D080 D090 D150*
VOL VOH
-- VDD - 0.7 --
-- -- --
0.6 -- 10.5
D100
I/O ports(2) (Includes CLKOUT) VOD Open Drain High Voltage Capacitive Loading Specs on Output Pins* Cosc2 OSC2 pin
--
--
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101 * Note 1: 2:
CIO
All I/O pins and OSC2 (in RC -- -- 50 pF mode) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin.
DS41171A-page 150
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
17.3
17.3.1
AC Characteristics: PIC16C781/782 (Industrial)
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp ck CLKOUT dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F H I L Fall High Invalid (Hi-impedance) Low P R V Z High Low Period Rise Valid Hi-impedance High Low
T
Time
osc t0 t1
OSC1 T0CKI T1CKI
FIGURE 17-3:
LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS
CL
Pin VSS
CL
RL = 464 CL = 50 pF 15 pF for all pins except OSC2 for OSC2 output
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 151
PIC16C781/782
17.3.2 TIMING DIAGRAMS AND SPECIFICATIONS CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 15 new value 19 18 12 16 11 Q1 Q2 Q3
FIGURE 17-4:
20, 21 Note 1: Refer to Figure 17-3 for load conditions.
TABLE 17-3:
Parameter No.
10* 11* 12* 13* 14* 15* 16* 17* 18*
CLKOUT AND I/O TIMING REQUIREMENTS
Sym Characteristic
OSC1 to CLKOUT OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port output rise time Port output fall time INT pin high or low time RB7:RB0 change INT high or low time
PIC16C781/782 PIC16LC781/782
Min
-- -- -- -- -- 0.25TCY + 25 0 -- 100 200 0 -- -- -- -- TCY TCY
Typ
75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- -- --
Max
200 200 100 100 0.5TCY + 20 -- -- 150 -- -- -- 25 60 25 60 -- --
Units Conditions
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TOSH2CKL TOSH2CKH TCKR TCkF TCKL2IOV TIOV2CKH TCKH2IOl TOSH2IOV TOSH2IOl
19* 20* 21* 22* 23* *
TIOV2OSH TIOR TIOF TINP TRBP
Port input valid to OSC1 (I/O in setup time)
PIC16C781/782 PIC16LC781/782 PIC16C781/782 PIC16LC781/782
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
DS41171A-page 152
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
FIGURE 17-5: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 CLKOUT 3 3 4 4
TABLE 17-4:
Parameter No. 1A
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency(1) Min DC DC DC DC 0.1 4 5 250 50 50 5 250 50 5 200 100 2.5 15 -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- TCY -- -- -- -- -- -- Max 4 20 20 200 4 20 200 -- -- -- -- 10,000 250 -- DC -- -- -- 25 50 15 Units MHz MHz MHz kHz Conditions XT osc mode EC osc mode HS osc mode LP osc mode
Sym FOSC
Oscillator Frequency(1)
MHz XT osc mode MHz HS osc mode kHz LP osc mode ns ns ns s ns ns s ns ns s ns ns ns ns XT and RC osc mode EC osc mode HS osc mode LP osc mode XT osc mode HS osc mode LP osc mode TCY = 4/FOSC XT oscillator LP oscillator HS oscillator EC oscillator XT oscillator LP oscillator HS oscillator EC oscillator
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
2 3*
TCY TOSL, TOSH
Instruction Cycle Time(1) External Clock in (OSC1) High or Low Time
4*
TOSR, TOSF
External Clock in (OSC1) Rise or Fall Time
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
*
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 153
PIC16C781/782
TABLE 17-5: INTERNAL RC OSCILLATOR CALIBRATED FREQUENCIES PIC16C781/782, PIC16LC781/782
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40xC TA +85C (industrial) Operating Voltage VDD range is described in Section 17-1. Characteristic Internal Calibrated RC Frequency Internal Calibrated RC Frequency Min 3.65 3.55* Typ(1) 4.00 4.00 Max 4.28 4.31* Units Conditions
AC Characteristics Parameter No.
Sym
MHz VDD = 5.0V MHz VDD = 2.5V
* These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 17-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer Reset 34 I/O Pins 32 30
31 34
Note 1: Refer to Figure 17-3 for load conditions.
FIGURE 17-7:
BROWN-OUT RESET TIMING
VDD
BVDD 35
DS41171A-page 154
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
TABLE 17-6:
Parameter No. 30* 31* 32* 33* 34* 35*
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Sym Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset pulse width Min 2 7 -- 28 -- 100 Typ -- 18 1024 TOSC 72 -- -- Max -- 33 -- 132 2.1 -- Units s ms -- ms s s VDD VBOR (D005) Conditions VDD = 5V, -40C to +85C VDD = 5V, -40C to +85C TOSC = OSC1 period VDD = 5V, -40C to +85C
TMCL TWDT TOST TPWRT TIOZ TBOR
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 17-8:
BROWN-OUT RESET CHARACTERISTICS
VDD VBOR
(device not in Brown-out Reset)
(device in Brown-out Reset)
RESET (due to BOR)
72 ms time out
(1)
Note 1: Only if Power-up Timer is enabled. If Timer is disabled, time-out is 0 ms
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 155
PIC16C781/782
FIGURE 17-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
40
41
42 RA6/OSC2/CLKOUT/T1CKI
45
46
47 TMR0 or TMR1 Note: Refer to Figure 17-3 for load conditions.
48
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2001 Microchip Technology Inc.
PIC16C781/782
TABLE 17-7:
Param No. 40* 41* 42* Sym TTOH TTOL TTOP
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0.5TCY + 20 15 30
0.5Tcy + 20 15 30
Typ -- -- -- -- -- --
Max -- -- -- -- -- --
Units ns ns ns ns ns ns
Conditions Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47
45*
TT1H
T1CKI High Time Synchronous, Prescaler = 1 Synchronous, PIC16C781/782 Prescaler = 2,4,8 Asynchronous PIC16C781/782
-- -- --
-- -- --
-- -- --
-- -- --
ns ns ns
ns ns ns
45*
TT1H
T1CKI High Time Synchronous, Prescaler = 1
PIC16LC781/782 Synchronous, Prescaler = 2,4,8
Must also meet parameter 47
Asynchronous 46* TT1L T1CKI Low Time
PIC16LC781/782
Synchronous, Prescaler = 1 Synchronous, PIC16C781/782 Prescaler = 2,4,8 Asynchronous PIC16C781/782
0.5TCY + 20 15 30
0.5TCY + 20 15 30
-- -- --
-- -- --
-- -- --
-- -- --
ns ns ns
ns ns ns
Must also meet parameter 47
46*
TT1L
T1CKI Low Time
Synchronous, Prescaler = 1
PIC16LC781/782 Synchronous, Prescaler = 2,4,8
Must also meet parameter 47
Asynchronous 47* TT1P T1CKI input period Synchronous
PIC16LC781/782
PIC16C781/782
Greater of: 30 OR TCY + 40 N 60 Greater of: 30 OR TCY + 40 N
60
--
--
ns
N = prescale value (1, 2, 4, 8)
Asynchronous 47* TT1P T1CKI input period Synchronous
PIC16C781/782
PIC16LC781/782
--
--
--
--
ns
ns
N = prescale value (1, 2, 4, 8)
Asynchronous FT1 48* *
PIC16C781/782
--
--
ns
Timer1 oscillator input frequency range (oscillator enabled by setting bit T1OSCEN)
DC
--
50
kHz
-- 7TOSC -- Tcke2tmrl Delay from external clock edge to timer increment 2TOSC These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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17.4 Operational Amplifier
DC CHARACTERISTICS: OPERATIONAL AMPLIFIER (OPA)
Standard Operating Conditions (unless otherwise stated): VDD = 2.7V to 5.5V, TA = 25C, VCM = VDD/2, RL = 100 k to VDD/2, and VOUT ~ VDD/2 Operating Temperature -40C to +85C for Industrial Symbol Min Typ Max Units Conditions
TABLE 17-8:
DC CHARACTERISTICS
Param No.
Parameters Input Offset Voltage Input Offset Voltage Input Offset Voltage Input Offset Voltage Input Current and Impedance Input Bias Current Input Offset Bias Current Common Mode Common Mode Input Range Common Mode Rejection Open Loop Gain DC Open Loop Gain DC Open Loop Gain
VOS VOS IB IOS VCM CMR AOL AOL
TBD TBD -50 -- VSS TBD -- --
2 100 -- 1 -- 80 90 80
TBD TBD +50 -- VDD-1.4 -- -- --
mV V nA pA V dB dB dB
Prior to Auto Calibration Following Auto Calibration Following Auto Calibration Following Auto Calibration VDD = 5 V VCM = VDD/2, Frequency = DC GBWP = 1 following Auto Calibration RL = 25 k connected to VDD/2, 50 mV < VOUT < VDD - 50 mV RL = 5 k connected to VDD/2, 100 mV < VOUT < VDD - 100 mV GBWP = 0 following Auto Calibration RL = 50 k connected to VDD/2, 50 mV < VOUT < VDD - 50 mV RL = 100 k connected to VDD/2, 50 mV < VOUT < VDD - 50 mV GBWP = 1 Following Auto Calibration RL = 5 k connected to VDD/2 VDD = 5 V
DC Open Loop Gain DC Open Loop Gain
AOL AOL
-- --
TBD TBD
-- --
dB dB
Output Output Voltage Swing Output Short Circuit Current Power Supply Power Supply Rejection Auto Calibration Reference
VOUT ISC PSR ACR
VSS+0.1 -- -- TBD
-- 25 80 1.2
VDD-0.1 TBD -- TBD
V mA dB V
Following Auto Calibration CALREF = 0
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PIC16C781/782
TABLE 17-9: AC CHARACTERISTICS: OPERATIONAL AMPLIFIER (OPA)
Standard Operating Conditions (unless otherwise stated): VDD = 2.7V to 5.5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 100k to VDD/2, and VOUT = VDD/2 Operating Temperature -40C to +85C for Industrial Symbol Min Typ Max Units Conditions
AC CHARACTERISTICS
Param No.
Parameters Gain Bandwidth Product
GBWP GBWP Input Offset Auto Calibration Time Turn On Time Phase Margin Slew Rate Note: TZ TZ TON TON M M SR SR
-- -- -- -- -- -- -- -- -- --
75 2 300 TBD 10 TBD TBD TBD TBD TBD
-- --
kHz MHz s s s s
VDD = 5V, GBWP = 0 VDD = 5V, GBWP = 1 VDD = 5V, GBWP = 1 VDD = 5V GBWP = 0 VDD = 5V, GWBP = 1 VDD = 5V, GBWP = 0
TBD TBD TBD TBD -- -- -- --
degrees VDD = 5V, GBWP = 0 degrees VDD = 5V, GBWP = 1 V/s V/s VDD = 5V, GBWP = 0 VDD = 5V, GBWP = 1
Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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DS41171A-page 159
PIC16C781/782
17.5 Comparators
TABLE 17-10: DC CHARACTERISTICS: VOLTAGE COMPARATORS C1 AND C2
DC CHARACTERISTICS Param No. Standard Operating Conditions (unless otherwise stated): VDD = 2.7V to 5.5V, TA = 25C, VCM = VDD/2 Operating Temperature -40C to +85C for Industrial Symbol VOS Min TBD TBD TBD
--
Parameters Input Offset Voltage Input Current and Impedance Input Bias Current Input Offset Bias Current Common Mode Common Mode Input Range Common Mode Rejection Open Loop Gain DC Open Loop Gain Power Supply Rejection
Typ 1 2.5
--
Max TBD TBD -- TBD VDD1.4V
-- --
Units mV mV nA nA V dB dB dB
Conditions C1SP = 1, C2SP = 1 C1SP = 0, C2SP = 0
IB IOS VCM CMR AOL PSR
TBD
--
VSS
--
70 90 TBD
VDD = 5V VCM = VDD/2, Frequency = DC
--
--
VDD = 5V
TABLE 17-11: AC CHARACTERISTICS: COMPARATORS C1 AND C2
AC CHARACTERISTICS Param No. Standard Operating Conditions (unless otherwise stated): VDD = 2.7V to 5.5V, TA = 25C, VCM = VDD/2 Operating Temperature -40C to +85C for Industrial Symbol Min Typ Max Units Conditions
Parameters Response Time Response Time
tr
--
75
--
ns
tr
--
0.5
--
s
tr
--
100
TBD
ns
tr
--
0.5
TBD
s
VDD = 5V, C1SP = 1, C2SP = 1, Comparator output signal is for internal use only, Input overdrive = 10 mV, step = 110 mV, VCM = VDD/2. VDD = 5V, C1SP = 0, C2SP = 0, Comparator output signal is for internal use only, Input overdrive = 10 mV, step = 110 mV, VCM = VDD/2. VDD = 5 , CL = 100 pF, C1SP = 1, C2SP = 1, Comparator output is available on I/O pin, Input overdrive = 10 mV, step = 110 mV, VCM = VDD/2. VDD = 5 , CL = 100 pF, C1SP = 0, C2SP = 0, Comparator output is available on I/O pin, Input overdrive = 10 mV, step = 110 mV, VCM = VDD/2. C1SP = 0, C2SP = 0, VDD = 5V C1SP = 1, C2SP = 1, VDD = 5V
Turn On Time
TON
-- --
10 TBD
TBD TBD
s s
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Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
17.6 Digital-to-Analog Converter (DAC)
TABLE 17-12: DC CHARACTERISTICS: DIGITAL-TO-ANALOG CONVERTER (DAC)
Standard Operating Conditions (unless otherwise stated): DC CHARACTERISTICS VDD = 2.7V to 5.5V, TA = 25C VDD = 5V, DACREF = 5V Operating Temperature -40C to +85C for Industrial Symbol RES INL DNL(1)
(1)
Param No.
Parameters Resolution Transfer Function Accuracy Integral Non-Linearity Error Differential Non-Linearity Error Offset Error Gain Error DACREF Input Characteristics DACREF Input Impedance DACREF Input Max Voltage Output Characteristics Output Voltage Range
Min
Typ 8
Max
Units bits
Conditions
VDD = 5V, DACREF = 5V TBD TBD TBD TBD TBD TBD VSS+.05 VSS+0.1 .25 .10 2.5 .25 100 -- -- -- VDD-0.1 2 TBD TBD TBD TBD TBD TBD TBD -- VDD VDD0.05 LSb LSb mV LSb k V V V mA VDD = 5V RL = 100 k to VDD/2 VDD = 5V RL = 25 k to VDD/2 VDD = 5V VDD 3V VDAC = VDD/2 VDD = 5V
RREF VMAX VOUT
Output Short Circuit Current Output Series Resistance Power Supply Power Supply Current * Characterized, but not tested. Note 1: Calculated using end point method.
ISC* RO*
-- -- -- --
IDAC
250
TBD
A
TABLE 17-13: AC CHARACTERISTICS: DIGITAL-TO-ANALOG CONVERTER (DAC)
AC CHARACTERISTICS Param No. Standard Operating Conditions (unless otherwise stated): VDD = 2.7 V to 5.5 V, TA = 25C Operating Temperature-40C to +85C for Industrial Symbol Min Typ Max Units Conditions
Parameters Output Characteristics Slew Rate Settling Time
SR TS
-- --
1 5
--
V/s VDD = 5 V, CL = 50 pF s s VDD = 5 V, CL = 50 pF Settling time to 1/2 LSb for 10%FS to 90%FS step VDD = 5 V
10
Turn On Time
TON
--
10
TBD
Note 1: Data in `Typ' column is at 5V, 25 C unless otherwise stated. These parameters are for design guidance only and are not tested.
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DS41171A-page 161
PIC16C781/782
17.7
17.7.1
Analog Peripherals Characteristics
BANDGAP VOLTAGE
Bandgap voltage is used as the reference voltage in the PBOR, PLVD, Auto Calibration, and VR modules
FIGURE 17-10: BANDGAP START-UP TIME
VBGAP VBGAP = 1.32V (internal use only)
Enable Bandgap Bandgap Stable TBGAP
TABLE 17-14: BANDGAP START-UP TIME
Parameter No. 36* Sym Characteristic Min -- Typ 30 Max -- Units s Conditions Defined as the time between the instant that the bandgap is enabled and the moment that the bandgap reference voltage is stable.
TBGAP Bandgap start-up time
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
17.7.2
VR MODULE
TABLE 17-15: DC CHARACTERISTICS: VR
DC CHARACTERISTICS Param No. D400 D402* D404* D405* D406* D407* * Symbol VR TCVOUT IVREFSO IVREFSI CL* DVOUT/ DIOUT DVOUT/ DVDD Characteristic Output Voltage Output Voltage Temperature Coefficient External Load Source External Load Sink External Capacitor Load Load Regulation Supply Regulation Standard Operating Conditions (unless otherwise stated): Operating temperature -40C TA +85C for industrial Operating voltage VDD as described in Section 17.1 Min
-- -- -- -- -- -- -- --
Typ 3.072 TBD
-- -- --
Max
--
Units V ppm/C mA mA pF mV/mA mV/V
Conditions VDD 3.5V
TBD 5 -5 200 TBD TBD 1
1 1
--
ISOURCE = 0 mA to 5 mA ISINK = 0 mA to 5 mA
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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17.7.3 PROGRAMMABLE LOW VOLTAGE DETECT MODULE (PLVD)
TABLE 17-16: LOW VOLTAGE DETECT CHARACTERISTICS
VDD
VLVD
(LVDIF set by hardware) LVDIF (LVDIF can be cleared in software anytime during the gray area)
TABLE 17-17: ELECTRICAL CHARACTERISTICS: PLVD
DC CHARACTERISTICS Param No. D420* Characteristic PLVD Voltage Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Operating voltage VDD range as described in DC spec Section 17-1. Symbol Min Typ Max Units Conditions
LV = 0100 VPLVD 2.35 -- 2.80 V -- LV = 0101 2.55 -- 3.02 V -- LV = 0110 2.64 -- 3.14 V -- LV = 0111 2.83 -- 3.37 V -- LV = 1000 3.11 -- 3.71 V -- LV = 1001 3.29 -- 3.93 V -- LV = 1010 3.39 -- 4.04 V -- LV = 1011 3.58 -- 4.26 V -- LV = 1100 3.77 -- 4.49 V -- LV = 1101 3.95 -- 4.71 V -- LV = 1110 4.23 -- 5.05 V -- Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Production tested at TAMB = 25C. Specifications over temperature limits ensured by characterization.
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17.7.4 PROGRAMMABLE BROWN-OUT RESET MODULE DC CHARACTERISTICS: PBOR
Standard Operating Conditions (unless otherwise stated): Operating temperature-40C TA +85C for Industrial Operating voltage VDD range as described in DC spec Section 17-1. Symbol VBOR Min 2.35 2.55 3.95 4.23 Typ -- -- -- -- Max 2.80 3.02 4.71 5.05 Units V Conditions
-- -- -- --
DC CHARACTERISTICS Param No. D005*
Characteristic BOR Voltage BORV<1:0> = 11 BORV<1:0> = 10 BORV<1:0> = 01 BORV<1:0> = 00
TABLE 17-18: ADC CONVERTER CHARACTERISTICS PIC16C781/782
Param No. A01 A02 NR EABS Sym Characteristic Resolution Absolute Error Min -- -- -- A03 INL Integral Now Linearity Error -- -- A04 DNL Differential Now Linearity Error Gain Error -- -- A05 GN -- -- A06 EOFF Offset Error -- -- A10 A20 A25 A30 A40 A50 -- ADCREF VAIN ZAIN IADC IREF Monotonicity Reference Voltage Analog Input Voltage Recommended Impedance of Analog Voltage Source ADC Conversion Current (VDD) ADCREF Input Current(2) -- 3.0V VSS - 0.3 -- -- 10 Typ -- -- -- -- -- -- -- -- -- -- -- guaranteed -- -- -- 180 --
(4)
Max 8 < 1 < 2 < 1 < 2 < 1 < 2 < 1 < 2 < 1 < 2 -- VDD + 0.3 ADCREF 10.0 -- 1000
Units bits LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb -- V V k A A
Conditions ADCREF = AVDD = 5.12V, VSS VAIN ADCREF ADCREF = AVDD = 5.12V, VSS VAIN ADCREF ADCREF = AVDD = 3.0V(3) ADCREF = AVDD = 5.12V, VSS VAIN ADCREF ADCREF = AVDD = 3.0V(3) ADCREF = AVDD = 5.12V, VSS VAIN ADCREF ADCREF = AVDD = 3.0V(3) ADCREF = AVDD = 5.12V, VSS VAIN ADCREF ADCREF = AVDD = 3.0V(3) ADCREF = AVDD = 5.12V, VSS VAIN ADCREF ADCREF = AVDD = 3.0V(3) VSS VAIN ADCREF
-- -- --
Average current consumption when ADC is on.(1) During VAIN acquisition. Based on differential of VHOLD to VAIN. To charge CHOLD, see Section 9.3. During ADC Conversion cycle.
-- * Note 1: 2: 3: 4:
--
40
A
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. When ADC is off, it will not consume any current other than minor leakage current. The power-down current specification (D020A) includes any such leakage from the ADC module. ADCREF current is from RA3/AN3/VREF1 pin or AVDD pin, whichever is selected as reference input. These specifications apply if ADCREF = 3.0 V and if AVDD 3.0 V. VAIN must be between VSS and ADCREF. The A/D conversion result never decreases with an increase in the Input Voltage and has no missing codes.
DS41171A-page 164
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PIC16C781/782
FIGURE 17-11: ADC CONVERSION TIMING
BSF ADCON0, GO (TOSC/2)(1) Q4 130 ADC CLK 132 131
1 TCY
ADC DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO/DONE SAMPLING STOPPED CONVERSION COMPLETE
SAMPLE
Note
1:
If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.
TABLE 17-19: ADC CONVERSION REQUIREMENTS
Param No. 130 Sym TAD Characteristic ADC clock period ADC Internal RC Oscillator Period
(2)
Min 2.0 TBD --
Typ 4.0 TBD 9.5 20
Max 6.0 TBD -- -- --
Units s s TAD s s
Conditions ADC RC mode
PIC16C781/782 PIC16LC781/782
131 132
TCNV TACQ
Conversion time (not including S/H time)(1) Acquisition time
5*
--
The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 19.5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to ADC clock start
--
TOSC/2
--
--
135 *
TSWC
Switching from convert sample time
1.5
--
--
TAD
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These specifications ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 13.1 for min. conditions.
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Preliminary
DS41171A-page 165
PIC16C781/782
NOTES:
DS41171A-page 166
Preliminary
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18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. In some graphs or tables the data presented is outside specified operating range (e.g., outside specified VDD range.). This is for information only and devices are ensured to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. Standard deviation is denoted by sigma ( ). Typ or Typical represents the mean of the distribution at 25C. Max or Maximum represents the mean +3 over the temperature range of -40C to 85C. Min or Minimum represents the mean -3 over the temperature range of -40C to 85C. Graphs and Tables are not available at this time.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 167
PIC16C781/782
NOTES:
DS41171A-page 168
Preliminary
2001 Microchip Technology Inc.
PIC16C781/782
19.0
19.1
PACKAGING INFORMATION
Package Marking Information
20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example PIC16C781 -I/SS 0107017
20-Lead CERDIP Windowed XXXXXXXX XXXXXXXX YYWWNNN
Example PIC16C781 /JW 0105017
20-Lead SOIC XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
Example PIC16C781/SO
0110017
20-Lead PDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example PIC16C781-I/P 0110017
Legend:
XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
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Preliminary
DS41171A-page 169
PIC16C781/782
20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
E E1 p
D
B n
2 1
c A
A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
.068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0
INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .013 5 5
MAX
MIN
.078 .072 .010 .322 .212 .289 .037 .010 8 .015 10 10
MILLIMETERS NOM 20 0.65 1.73 1.85 1.63 1.73 0.05 0.15 7.59 7.85 5.11 5.25 7.06 7.20 0.56 0.75 0.10 0.18 0.00 101.60 0.25 0.32 0 5 0 5
MAX
1.98 1.83 0.25 8.18 5.38 7.34 0.94 0.25 203.20 0.38 10 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072
DS41171A-page 170
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2001 Microchip Technology Inc.
PIC16C781/782
20-Lead CERDIP Windowed
Diagram not available at this time.
2001 Microchip Technology Inc.
Preliminary
DS41171A-page 171
PIC16C781/782
20-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E E1 p
D
2 B n 1
h 45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.093 .088 .004 .394 .291 .496 .010 .016 0 .009 .014 0 0
INCHES* NOM 20 .050 .099 .091 .008 .407 .295 .504 .020 .033 4 .011 .017 12 12
MAX
MIN
.104 .094 .012 .420 .299 .512 .029 .050 8 .013 .020 15 15
MILLIMETERS NOM 20 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 12.60 12.80 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12
MAX
2.64 2.39 0.30 10.67 7.59 13.00 0.74 1.27 8 0.33 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-094
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2001 Microchip Technology Inc.
PIC16C781/782
20-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D
2 n E 1
A
A2
c A1 eB Units Dimension Limits n p B INCHES* NOM 20 .100 .155 .130 B1 p MILLIMETERS NOM 20 2.54 3.56 3.94 2.92 3.30 0.38 7.49 7.87 6.10 6.35 26.04 26.24 3.05 3.30 0.20 0.29 1.40 1.52 0.36 0.46 7.87 9.40 5 10 5 10
L
MIN
MAX
MIN
MAX
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .295 .310 .325 Molded Package Width E1 .240 .250 .260 Overall Length D 1.025 1.033 1.040 Tip to Seating Plane L .120 .130 .140 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .055 .060 .065 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-019
4.32 3.68 8.26 6.60 26.42 3.56 0.38 1.65 0.56 10.92 15 15
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NOTES:
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PIC16C781/782
INDEX A
ADC Accuracy/Error ............................................................ 75 Connection Considerations......................................... 76 Conversion Time ......................................................... 75 Converter Characteristics ......................................... 164 Effects of a RESET ..................................................... 76 Faster Conversion - Lower Resolution Trade-off ........ 75 Flow Chart of ADC Operation ..................................... 77 References.................................................................. 76 Transfer Function ........................................................ 76 ADC Acquisition Requirements........................................... 73 ADC Conversion Clock ....................................................... 72 ADC Minimum Charging Time ............................................ 73 ADC Operation During SLEEP ........................................... 75 Analog Signal Multiplexing Diagram ..................................... 7 Analog-to-digital Converter (ADC) Module ......................... 69 Analog-to-Digital Converter Module Control Registers ........................................................ 70 Assembler MPASM Assembler ................................................... 141 BOR DC Characteristics.................................................... 164 BOR. See Brown-out Reset Brown-out Reset (BOR).................................... 117, 125, 126 Buck Configuration LC Power Supply............................... 112 Buck LC Switching Power Supply..................................... 110
C
C1 Input to PSMC w/DAC as Reference ............................ 95 C2 Configuration Program .................................................. 95 CALCON Register .............................................................. 84 Calculating the Minimum Required Acquisition Time ................................................................. 73 Clock Noise......................................................................... 76 Code Examples Doing an ADC Conversion ......................................... 74 Code Protection ................................................................ 117 Comparator C1 Control Register ........................................ 89 Comparator C2 Configuration With Output Synchronized to T1CKI....................................................... 95 Comparator C2 Control Registers ...................................... 92 Comparator C2 Synchronized to T1CKI ............................. 95 Comparator Configuration .................................................. 95 Comparator Module ............................................................ 89 Associated Registers.................................................. 98 Control Registers........................................................ 89 Effects of a RESET..................................................... 98 Output State Versus Input Conditions......................... 89 Configuration as OPAMP or Comparator ........................... 86 Configuration Bits ............................................................. 117 Configuration of Comparator C1 with DAC......................... 96 Configuring the ADC Module .............................................. 72 Configuring the Reference Voltages................................... 72 Control Register CM2CON0 ............................................... 92 Control Register T1CON..................................................... 56
B
Banking, Data Memory ....................................................... 17 Block Diagrams ADC Module................................................................ 69 Auto Calibration Module.............................................. 85 Comparator C1 Simplified........................................... 90 Comparator C2 Simplified........................................... 90 DAC Converter............................................................ 80 Low Voltage Detect ..................................................... 64 On-Chip Reset Circuit ............................................... 121 OPA Module................................................................ 83 PIC16C781 ................................................................... 5 PIC16C782 ................................................................... 6 PSMC Module in Dual Alternating Output PWM Mode ............................................................... 100 PSMC Module in Single Output PSM Mode ............. 102 PSMC Module in Single Output PWM Mode .............. 99 RA0/AN0/OPA+ Pin .................................................... 27 RA1/AN1/OPA- Pin ..................................................... 28 RA2/AN2/VREF2 Pin .................................................. 29 RA3/AN3/VREF1 Pin .................................................. 30 RA4/T0CKI Pin............................................................ 31 RA5/MCLR/VPP.......................................................... 32 RA6/OSC2/CLKOUT/T1CKI Pin ................................. 33 RA7/OSC1/CLKIN Pin ................................................ 34 RB0/INT/AN4/VR Pin .................................................. 37 RB1/AN5/VDAC Pin.................................................... 38 RB2/AN6 Pin............................................................... 39 RB3/AN7/OPA Pin ...................................................... 40 RB4 Pin....................................................................... 41 RB5 Pin....................................................................... 42 RB6/C1/PSMC1A Pin ................................................. 43 RB7/C2/PSMC1B/T1G Pin ......................................... 44 RC Oscillator Mode................................................... 120 Timer0 ......................................................................... 51 Timer0/WDT Prescaler................................................ 53 TIMER1....................................................................... 58 Watchdog Timer (WDT) ............................................ 130 Boost LC Switching Power Supply.................................... 107
D
DAC Configuration.............................................................. 81 DAC Module Accuracy/Error............................................................ 81 Associated Registers/Bits ........................................... 81 DAC Transfer Function ............................................... 81 Differential Non-Linearity Error ................................... 81 Effects of a RESET..................................................... 81 Gain Error ................................................................... 81 Integral Non-Linearity Error ........................................ 81 Monotonicity ............................................................... 81 Offset Error ................................................................. 81 Data Memory Bank Select (RP Bits) ................................................. 17 Data Memory Organization................................................. 11 Register File Map ....................................................... 12 DC Characteristics PIC16C781/782, PIC16LC781/782 (Industrial)......................................................... 149 Development Support ....................................................... 141 Device Overview................................................................... 5 Digital-to-Analog Converter (DAC) Module......................... 79 Control Registers........................................................ 79 Direct Addressing ............................................................... 24
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E
EC Mode ........................................................................... 119 Effect of RESET on Core Registers .................................... 24 Summary..................................................................... 24 Effects of RESET ................................................................ 52 Electrical Characteristics................................................... 147 Errata .................................................................................... 3 Examples DAC Configuration ...................................................... 81 OPAMP Calibration Mode Configuration..................... 86 Peripheral Configuration ........................................... 113 PSMC Configuration ................................................. 109 PSMC Configuration Example for a Buck Mode Switching Power Supply ................................. 111 Window Comparator ................................................... 97 External Power-on Reset Circuit ....................................... 122 SUBLW ..................................................................... 139 SUBWF..................................................................... 139 SWAPF ..................................................................... 139 XORLW..................................................................... 139 XORWF .................................................................... 140 INT Interrupt (RB0/INT/AN4/VR). See Interrupt Sources INTCON Register GIE Bit ........................................................................ 19 INTE Bit ...................................................................... 19 INTF Bit ...................................................................... 19 PEIE Bit ...................................................................... 19 RBIE Bit ...................................................................... 19 RBIF Bit ...................................................................... 19 T0IE Bit ....................................................................... 19 T0IF Bit ....................................................................... 19 Interrupt Sources ...................................................... 117, 128 RB0/INT Pin, External............................................... 128 TMR0 Overflow................................................... 52, 129 Interrupts, Context Saving During..................................... 129 Interrupts, Enable Bits Global Interrupt Enable (GIE Bit) .............................. 128 Interrupt-on-Change (RB7:RB0) Enable (RBIE Bit).................................................................. 129 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) .................................................................. 129 TMR0 Overflow Flag (T0IF Bit)................................. 129
F
Firmware Instructions........................................................ 133 FSR Register....................................................................... 15
G
General Purpose Register File............................................ 13
I
I/O Port Analog/Digital Mode............................................... 25 I/O Ports .............................................................................. 25 ICEPIC In-Circuit Emulator ............................................... 142 ID Locations ...................................................................... 117 In-Circuit Serial Programming (ICSP) ............................... 117 Indirect Addressing ............................................................. 24 Initialization Condition for All Registers............................. 126 Initializing Timer0 ................................................................ 51 Instruction Format ............................................................. 133 Instruction Set ................................................................... 133 ADDLW ..................................................................... 135 ADDWF ..................................................................... 135 ANDLW ..................................................................... 135 ANDWF ..................................................................... 135 BCF ........................................................................... 135 BSF ........................................................................... 135 BTFSC ...................................................................... 136 BTFSS ...................................................................... 135 CALL ......................................................................... 136 CLRF......................................................................... 136 CLRW........................................................................ 136 CLRWDT................................................................... 136 COMF ....................................................................... 136 DECF ........................................................................ 136 DECFSZ.................................................................... 137 GOTO........................................................................ 137 INCF.......................................................................... 137 INCFSZ ..................................................................... 137 IORLW....................................................................... 137 IORWF ...................................................................... 137 MOVF........................................................................ 138 MOVLW..................................................................... 138 MOVWF .................................................................... 138 NOP .......................................................................... 138 RETFIE ..................................................................... 138 RETLW...................................................................... 138 RETURN ................................................................... 138 RLF ........................................................................... 138 RRF........................................................................... 139 SLEEP ...................................................................... 139
K
KEELOQ Evaluation and Programming Tools .................... 144
L
Low Power Window Comparator with Interrupt .................. 96 Low Voltage Detect Associated Register Summary ................................... 67 Low Voltage Detect Registers ............................................ 67 Low Voltage Detect Waveforms ......................................... 65 LP, XT and HS Modes ...................................................... 119
M
Master Clear (MCLR) MCLR Reset, Normal Operation....................... 125, 126 MCLR Reset, SLEEP................................ 121, 125, 126 Memory Organization ......................................................... 11 MPLAB C17 and MPLAB C18 C Compilers ..................... 141 MPLAB ICD In-Circuit Debugger ...................................... 143 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ................................ 142 MPLAB Integrated Development Environment Software ...................................................... 141 MPLINK Object Linker/MPLIB Object Librarian ................ 142
O
OPA Auto Calibration.......................................................... 83 OPA Module Associated Registers .................................................. 87 Common Mode Voltage Range................................... 86 Effects of a RESET ..................................................... 86 Gain Bandwidth Product ............................................. 86 Input Offset Voltage .................................................... 86 Leakage Current ......................................................... 86 Open Loop Gain ......................................................... 86 OPA Offset Voltage ............................................................ 84 OPCODE Field Descriptions............................................. 133 Operational Amplifier (OPA) Module .................................. 83
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OPTION_REG Register INTEDG Bit ................................................................. 18 PS Bits .................................................................. 18, 52 PSA Bit.................................................................. 18, 52 RBPU Bit..................................................................... 18 T0CS Bit................................................................ 18, 51 T0SE Bit................................................................ 18, 51 Oscillator Configuration..................................................... 119 CLKOUT ................................................................... 120 Dual Speed Operation for INTRC Modes.................. 120 EC ..................................................................... 119, 123 ER ............................................................................. 119 HS ..................................................................... 119, 123 INTRC ............................................................... 119, 123 LP...................................................................... 119, 123 XT ..................................................................... 119, 123 Oscillator, WDT ................................................................. 129 Oscillators RC, Block Diagram ................................................... 120 OTP Program Memory Read .............................................. 49 PIR1 Register ADIF Bit ...................................................................... 21 C1IF Bit....................................................................... 21 C2IF Bit....................................................................... 21 LVDIF Bit .................................................................... 21 TMR1IF Bit ................................................................. 21 PLVD DC Characteristics.................................................... 163 PLVD Example ................................................................... 67 PMCON1 ............................................................................ 47 PMDATH and PMDATL Registers...................................... 47 PMR Associated Register Summary ................................... 50 Pointer, FSR ....................................................................... 23 POR. See Power-on Reset PORTA Associated Register Summary ................................... 34 Initialization................................................................. 26 PORTA and the TRISA Register ........................................ 26 PORTB Associated Register Summary ................................... 45 Initialization................................................................. 35 Pull-up Enable (RBPU Bit).......................................... 18 RB0/INT Edge Select (INTEDG Bit) ........................... 18 RB0/INT Pin, External .............................................. 128 RB7:RB0 Interrupt-on-Change Enable (RBIE Bit).................................................................. 129 RB7:RB4 Interrupt-on-Change ................................. 129 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit).................................................................. 129 PORTB and the TRISB Register ........................................ 35 PORTB Interrupt-on-Change .............................................. 35 PORTB Weak Pull-up ......................................................... 35 Postscaler, WDT................................................................. 52 Assignment (PSA Bit) ........................................... 18, 52 Rate Select (PS Bits)............................................ 18, 52 Switching Between Timer0 and WDT ......................... 52 Power-down Mode. See SLEEP Power-on Reset (POR)..................... 117, 121, 122, 125, 126 Oscillator Start-up Timer (OST) ................................ 117 Power Control (PCON) Register............................... 123 Power-down (PD Bit) .................................................. 17 Power-on Reset Circuit, External ............................. 122 Power-up Timer (PWRT) .................................. 117, 122 Time-out (TO Bit) ........................................................ 17 Time-out Sequence .................................................. 122 Time-out Sequence on Power-up ..................... 125, 127 Prescaler, Timer0 ............................................................... 52 Assignment (PSA Bit) ........................................... 18, 52 Rate Select (PS Bits)............................................ 18, 52 Switching Between Timer0 and WDT ......................... 52 Prescaler, Timer1 Select (T1CKPS1:T1CKPS0 Bits) .............................. 57 PRO MATE II Universal Device Programmer ................... 143 Program .............................................................................. 47 Program Counter PCL Register .............................................................. 23 PCLATH Register ............................................... 23, 129 Reset Conditions ...................................................... 125 Program Memory Paging ........................................................................ 23 Program Memory Map and Stack PIC16C781 ................................................................. 11 PIC16C782 ................................................................. 11 Program Memory Organization........................................... 11
P
Package Marking Information ........................................... 169 Paging, Program Memory ................................................... 23 PCON Register ................................................................. 123 BOR Bit ....................................................................... 22 OSCF Bit..................................................................... 22 POR Bit ....................................................................... 22 WDTON Bit ................................................................. 22 PICDEM 1 Low Cost PICmicro Demonstration Board ........................................................ 143 PICDEM 17 Demonstration Board .................................... 144 PICDEM 2 Low Cost PIC16CXX Demonstration Board ........................................................ 143 PICDEM 3 Low Cost PIC16CXXX Demonstration Board ........................................................ 144 PICSTART Plus Entry Level Development Programmer ................................................ 143 Pin Functions AVDD ............................................................................. 9 AVSS.............................................................................. 9 RA0/AN0/OPA+............................................................. 8 RA1/AN1/OPA- ............................................................. 8 RA2/AN2/VREF2 ............................................................ 8 RA3/AN3/VREF1 ............................................................ 8 RA4/T0CKI.................................................................... 8 RA5/MCLR/VPP............................................................. 8 RA6/OSC2/CLKOUT/T1CKI ......................................... 8 RA7/OSC1/CLKIN......................................................... 8 RB0/INT/AN4/VR ........................................................... 8 RB1/AN5/VDAC ............................................................. 8 RB2/AN6 ....................................................................... 8 RB3/AN7/OPA............................................................... 8 RB4 ............................................................................... 8 RB5 ............................................................................... 8 RB6/C1/PSMC1A.......................................................... 8 RB7/C2/PSMC1B/T1G.................................................. 9 VDD ............................................................................... 9 VSS................................................................................ 9 Pinout Description PIC16C781/782 ............................................................ 8
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Program Memory Read (PMR) ........................................... 47 Program Memory Read Cycle Execution ............................ 50 Programmable Brown-out Reset (PBOR) ................. 121, 122 Programmable Low Voltage Detect Module (PLVD).................................................................... 63 Control Register .......................................................... 63 Effects of a RESET ..................................................... 67 Operation .................................................................... 64 Operation During SLEEP ............................................ 67 Programmable Switch Mode Controller (PSMC)................. 99 Programming C1 for PSMC Feedback................................ 96 Programming, Device Instructions .................................... 133 PSMC Associated Registers ................................................ 115 Configuration............................................................. 107 Control Registers ...................................................... 104 Effects of SLEEP and RESET................................... 115 PSMC1A Operation in PSM Mode Using C1 Comparator Only ......................................................... 102 PSMC1A Output Sequence in PSM Mode Using C1 and C2 Comparators ......................................... 103 PSMC1A Output Sequence in PWM Mode Using C1 and C2 Comparators ......................................... 101 PSMC1A Output Sequence in PWM Mode Using C1 Comparator Only ............................................... 100 PSMCCON0 Register ....................................................... 104 PSMCCON1 Register ....................................................... 104 Pulse Skip Modulation (PSM) ........................................... 102 Pulse Width Modulation (PWM) .......................................... 99 Timer1 Control Register (T1CON) .............................. 57 Voltage Reference Control Register (REFCON)......... 61 Weak Pull-up PORTB ................................................. 36 Registers Associated with VR............................................. 61 Registers/Bits Associated with ADC ................................... 77 Reset ................................................................................ 121 Brown-out Reset (BOR). See Brown-out Reset (BOR) Power-on Reset (POR). See Power-on Reset (POR) Reset Conditions for PCON Register ....................... 125 Reset Conditions for Program Counter..................... 125 Reset Conditions for STATUS Register .................... 125 WDT Reset. See Watchdog Timer (WDT)
S
Setting up the PLVD Module .............................................. 65 Single or Dual Output ....................................................... 103 SLEEP .............................................................. 117, 121, 131 Slope Compensation ........................................................ 103 Slope Compensation (SC) Switch Operation.................... 103 Software Simulator (MPLAB SIM) .................................... 142 Special Features of the CPU ............................................ 117 Special Function Registers ................................................. 13 ADCON0 Register ...................................................... 13 ADCON1 Register ...................................................... 14 ADRES Register ......................................................... 13 ANSEL Register.......................................................... 14 CALCON Register ...................................................... 15 CM1CON0 Register.................................................... 15 CM2CON0 Register.................................................... 15 CM2CON1 Register.................................................... 15 DAC Register.............................................................. 15 DACON0 Register ...................................................... 15 FSR Register .................................................. 13, 14, 16 INDF Register ........................................... 13, 14, 15, 16 INTCON Register...................................... 13, 14, 15, 16 IOCB Register............................................................. 14 LVDCON Register....................................................... 14 OPACON Register ...................................................... 15 OPTION_REG Register........................................ 14, 16 PCL Register ............................................ 13, 14, 15, 16 PCLATH Register ..................................... 13, 14, 15, 16 PCON Register ........................................................... 14 PIE1 Register ............................................................. 14 PIR1 Register ............................................................. 13 PMADRH Register...................................................... 15 PMADRL Register ...................................................... 15 PMCON1 Register ...................................................... 16 PMDATH Register ...................................................... 15 PMDATL Register ....................................................... 15 PORTA Register ......................................................... 13 PORTB Register ................................................... 13, 15 PSMCCON0 Register ................................................. 15 PSMCCON1 Register ................................................. 15 REFCON Register ...................................................... 14 STATUS Register...................................... 13, 14, 15, 16 Summary .................................................................... 13 T1CON Register ......................................................... 13 TMR0 Register...................................................... 13, 15 TMR1H Register ......................................................... 13 TMR1L Register.......................................................... 13 TRISA Register........................................................... 14 TRISB Register..................................................... 14, 16 WPUB Register........................................................... 14 Stack................................................................................... 23 STATUS Register ............................................................. 129
R
Read with Code Protect Set................................................ 50 Reading the EPROM Program Memory.............................. 49 Registers ADC Control Register (ADCON1) ............................... 71 ADC Control Register 0 (ADCON0) ............................ 70 ADC Result Register (ADRES) ................................... 71 Analog Select .............................................................. 25 Calibration Control Register (CALCON) ..................... 85 Comparator C1 Control Register0 (CM1CON0) ................................................................ 91 Comparator C2 Control Register0 (CM2CON0) ................................................................ 93 Comparator C2 Control Register1 (CM2CON1) ................................................................ 94 Digital-to-Analog Converter Control Register0 (DACON)..................................................................... 79 Digital-to-Analog Converter Register (DAC) ............... 79 INTCON ...................................................................... 19 Interrupt-on-Change PORTB ...................................... 36 OPAMP Control Register (OPACON).......................... 84 OPTION_REG............................................................. 18 PCON.......................................................................... 22 PIE1 ............................................................................ 20 Program memory Address High (PMADRH)............... 48 Program Memory Address Low (PMADRL) ................ 48 Program memory Data High (PMDATH) ..................... 47 Program Memory Data Low (PMDATL) ...................... 48 Program Memory Read Control Register 1 (PMCON1) .................................................................. 47 Programmable Low Voltage Detect Register (LVDCON) ................................................................... 66 PSMC Control Register0 (PSMCCON0) ................... 105 PSMC Control Register1 (PSMCCON1) ................... 106 STATUS ...................................................................... 17
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C Bit ............................................................................ 17 DC Bit.......................................................................... 17 IRP Bit......................................................................... 17 PD Bit.......................................................................... 17 RP Bits ........................................................................ 17 TO Bit .......................................................................... 17 Zero Bit ....................................................................... 17
V
Voltage Reference Module Effects of a RESET..................................................... 61 Voltage Reference Module (VR)......................................... 61
W
W Register ........................................................................ 129 Wake-up from SLEEP............................................... 117, 131 Interrupts .......................................................... 125, 126 MCLR Reset ............................................................. 126 Timing Diagram ........................................................ 132 WDT Reset ............................................................... 126 Watchdog Timer Associated Register Summary ................................. 130 Watchdog Timer (WDT)............................................ 117, 129 Enable (WDTE Bit) ................................................... 129 Postscaler. See Postscaler, WDT Programming Considerations ................................... 129 RC Oscillator ............................................................ 129 Time-out Period ........................................................ 129 WDT Reset, Normal Operation................. 121, 125, 126 WDT Reset, SLEEP ......................................... 125, 126 Window Comparator with Interrupt ..................................... 96 WWW, On-Line Support ....................................................... 3
T
T1CON Register T1CKPS1:T1CKPS0 Bits ............................................ 57 T1OSCEN Bit.............................................................. 57 TMR1CS Bit ................................................................ 57 TMR1ON Bit................................................................ 57 TAD vs. Device Operating Frequencies............................... 72 Timer0 ................................................................................. 51 Associated Registers .................................................. 53 Clock Source Edge Select (T0SE Bit)......................... 51 Clock Source Select (T0CS Bit)............................ 18, 51 Overflow Flag (T0IF Bit)............................................ 129 Overflow Interrupt ............................................... 52, 129 Prescaler. See Prescaler, Timer0 Timer0 Module .................................................................... 51 Timer0 Operation ................................................................ 51 Timer1 Associated Registers Summary.................................. 59 Clock Source Select (TMR1CS Bit) ............................ 57 Effects of a RESET ..................................................... 59 Module On/Off (TMR1ON Bit) ..................................... 57 Oscillator Enable (T1OSCEN Bit) ............................... 57 Timer1 Incrementing Edge.................................................. 58 Timer1 Initialization ............................................................. 55 Timer1 Interrupt .................................................................. 59 Timer1 Module Timer/Counter ............................................ 55 Timer1 Module with Gate Control ....................................... 55 Timer1 Operation ................................................................ 55 Timer1 Oscillator for the PIC16C781/782 ........................... 59 Timing Diagrams ADC Conversion ....................................................... 165 Brown-out Reset ....................................................... 154 CLKOUT and I/O....................................................... 152 External Clock........................................................... 153 External Clock Timing ............................................... 152 RESET, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer.................................................. 154 Time-out Sequence on Power-up ..................... 125, 127 Timer0 ....................................................................... 156 Timer0 and Timer1 External Clock............................ 156 Timer1 ....................................................................... 156 Wake-up from SLEEP via Interrupt ........................... 132 TRISA, ANSEL, and Control Precedence ........................... 26 TRISB, ANSEL, and Control Precedence ........................... 36 Typical Low Voltage Detect Application .............................. 63
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NOTES:
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ON-LINE SUPPORT
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013001
Connecting to the Microchip Internet Web Site
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2001 Microchip Technology Inc.
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READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C781/782 Questions: 1. What are the best features of this document? Y N Literature Number: DS41171A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
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8. How would you improve our software, systems, and silicon products?
DS41171A-page182
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PIC16C781/782 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a)
PIC16C781-I/P Industrial Temp., Plastic DIP package, normal VDD limits PIC16LC781-I/SS Industrial Temp., SSOP package, extended VDD limits PIC16C781-I/SOT Industrial Temp., SOIC package, Tape and Reel, normal VDD limits
b)
Device PIC16C781: VDD range 4.0V-5.5V PIC16C781T: VDD range 4.0V-5.5V (Tape and Reel) PIC16LC781: VDD range 2.7V-5.5V PIC16LC781T: VDD range 2.7V-5.5V (Tape and Reel)
c)
Temperature Range
I
=
-40C to +85C
Package
SO SS P JW
= = = =
SOIC SSOP PDIP Windowed CERDIP
Pattern
QTP, SQTP, ROM Code (factory specified) or Special Requirements . Blank for OTP and Windowed devices.
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2001 Microchip Technology Inc.
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WORLDWIDE SALES AND SERVICE
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Two Prestige Place, Suite 130 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
China - Shenzhen
Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086 Hong Kong Microchip Technology Hongkong Ltd. Unit 901, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Germany - Analog
Lochhamer Strasse 13 D-82152 Martinsried, Germany Tel: 49-89-895650-0 Fax: 49-89-895650-22
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
New York
150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
India
Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
06/01/01
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
DS41171A-page 184
Preliminary
2001 Microchip Technology Inc.

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